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TMS416100-80DGA Datasheet

  • TMS416100-80DGA

  • x1 Fast Page Mode DRAM

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TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 鈥?FEBRUARY 1994
鈥?/div>
鈥?/div>
鈥?/div>
This data sheet is applicable to all
TMS416100/Ps symbolized with Revision 鈥淏鈥?/div>
and subsequent revisions as described on
page 24.
Organization . . . 16 777 216
脳
1
Single 5-V Power Supply (鹵10% Tolerance)
Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME OR WRITE
tRAC
tCAC
tAA
CYCLE
(MAX )
(MAX )
(MAX )
(MIN)
60 ns
15 ns
30 ns
110 ns
70 ns
18 ns
35 ns
130 ns
80 ns
20 ns
40 ns
150 ns
DJ PACKAGE
( TOP VIEW )
DGA PACKAGE
( TOP VIEW )
V
CC
D
NC
W
RAS
A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
V
SS
Q
NC
CAS
NC
A9
A8
A7
A6
A5
A4
V
SS
V
CC
D
NC
W
RAS
A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
V
SS
Q
NC
CAS
NC
A9
A8
A7
A6
A5
A4
V
SS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?16100- 60
鈥?16100- 70
鈥?16100- 80
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Enhanced Page Mode Operation for Faster
Memory Access
CAS-Before-RAS Refresh
Long Refresh Period
鈥?4096 Cycle Refresh in 64 ms
(TMS416100)
鈥?256 ms for Extended Refresh Version
(TMS416100P)
3-State Unlatched Output
Low Power Dissipation (TMS416100P Only)
鈥?500-碌A CMOS Standby Current
鈥?500-碌A Self-Refresh Current
鈥?500-碌A Extended Refresh Battery Backup
Current
All Inputs, Outputs and Clocks Are TTL
Compatible
Operating Free-Air Temperature Range:
0擄C to 70擄C
PIN NOMENCLATURE
A0 鈥?A11
CAS
D
Q
NC
RAS
VCC
VSS
W
Address Inputs
Column-Address Strobe
Data In
Data Out
No Internal Connection
Row-Address Strobe
5-V Supply
Ground
Write Enable
description
The TMS416100/P series are high-speed, 16 777 216-bit dynamic random-access memories, organized as
16 777 216 words of one bit each. The TMS416100P series feature self refresh and extended refresh. They
employ state-of-the-art EPIC鈩?(Enhanced Performance Implanted CMOS) technology for high performance,
reliability, and low power at a low cost.
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All inputs, outputs, and clocks
are compatible with Series 74 TTL. All addresses and data-in lines are latched on chip to simplify system design.
Data out is unlatched to allow greater system flexibility.
The TMS416100/P are offered in 300-mil 24/26-lead plastic surface-mount SOJ packages (DJ suffix) and
24/26-lead plastic small-outline packages (DGA suffix). All packages are characterized for operation from 0擄C
to 70擄C.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1994, Texas Instruments Incorporated
POST OFFICE BOX 1443
Powered by ICminer.com Electronic-Library Service CopyRight 2003
鈥?/div>
HOUSTON, TEXAS 77251鈥?443
1

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