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TMS320C31 Datasheet

  • TMS320C31

  • DIGITAL SIGNAL PROCESSORS

  • 48頁(yè)

  • TI

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TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B 鈥?MARCH 1996 鈥?REVISED JANUARY 1999
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High-Performance Floating-Point Digital
Signal Processor (DSP):
鈥?TMS320C31-80 (5 V)
25-ns Instruction Cycle Time
440 MOPS, 80 MFLOPS, 40 MIPS
鈥?TMS320C31-60 (5 V)
33-ns Instruction Cycle Time
330 MOPS, 60 MFLOPS, 30 MIPS
鈥?TMS320C31-50 (5 V)
40-ns Instruction Cycle Time
275 MOPS, 50 MFLOPS, 25 MIPS
鈥?TMS320C31-40 (5 V)
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
鈥?TMS320LC31-40 (3.3 V)
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
鈥?TMS320LC31-33 (3.3 V)
60-ns Instruction Cycle Time
183.7 MOPS, 33.3 MFLOPS, 16.7 MIPS
32-Bit High-Performance CPU
16- / 32-Bit Integer and 32- / 40-Bit
Floating-Point Operations
32-Bit Instruction Word, 24-Bit Addresses
Two 1K
脳
32-Bit Single-Cycle Dual-Access
On-Chip RAM Blocks
Boot-Program Loader
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On-Chip Memory-Mapped Peripherals:
鈥?One Serial Port
鈥?Two 32-Bit Timers
鈥?One-Channel Direct Memory Access
(DMA) Coprocessor for Concurrent I/O
and CPU Operation
Fabricated Using 0.6
碌m
Enhanced
Performance Implanted CMOS (EPIC鈩?
Technology by Texas Instruments (TI鈩?
132-Pin Plastic Quad Flat Package
( PQ Suffix )
Eight Extended-Precision Registers
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Two Low-Power Modes
Two- and Three-Operand Instructions
Parallel Arithmetic / Logic Unit (ALU) and
Multiplier Execution in a Single Cycle
Block-Repeat Capability
Zero-Overhead Loops With Single-Cycle
Branches
Conditional Calls and Returns
Interlocked Instructions for
Multiprocessing Support
Bus-Control Registers Configure
Strobe-Control Wait-State Generation
description
The TMS320C31 and TMS320LC31 DSPs are 32-bit, floating-point processors manufactured in 0.6
碌m
triple-level-metal CMOS technology. The TMS320C31 and TMS320LC31 are part of the TMS320C3x
generation of DSPs from Texas Instruments.
The TMS320C3x鈥檚 internal busing and special digital-signal-processing instruction set have the speed and
flexibility to execute up to 80 million floating-point operations per second (MFLOPS). The TMS320C3x
optimizes speed by implementing functions in hardware that other processors implement through software or
microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.
The TMS320C3x can perform parallel multiply and ALU operations on integer or floating-point data in a single
cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs,
internal dual-access memories, one DMA channel supporting concurrent I / O, and a short machine-cycle time.
High performance and ease of use are results of these features.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and TI are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1999, Texas Instruments Incorporated
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈥?443
1

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