TMS320LF2402PZ Datasheet

IC型號：
TMS320LF2402PZ
PDF描述：
DSP CONTROLLERS
文件大小：
1341.10KB
PDF頁數：
106頁
芯片廠家：
TI

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TMS320LF2407, TMS320LF2406, TMS320LF2402

TMS320LC2406, TMS320LC2404, TMS320LC2402

DSP CONTROLLERS

SPRS094C 鈥?APRIL 1999 鈥?REVISED OCTOBER 1999

High-Performance Static CMOS Technology

鈥?33-ns Instruction Cycle Time (30 MHz)

鈥?30 MIPS Performance

鈥?Low-Power 3.3-V Design

Based on T320C2xx DSP CPU Core

鈥?Code-Compatible With 鈥橣243/鈥橣241/鈥機242

鈥?Instruction Set and Module Compatible

With 鈥橣240/鈥機240

鈥?Source-Code-Compatible With

TMS320C1x/2x

Flash (LF) and ROM (LC) Device Options

鈥?鈥橪F240x

鈥?/div>

: 鈥橪F2407, 鈥橪F2406, 鈥橪F2402

鈥?鈥橪C240x

鈥?/div>

: 鈥橪C2406, 鈥橪C2404, 鈥橪C2402

On-Chip Memory

鈥?Up to 32K Words x 16 Bits of Flash

EEPROM (4 Sectors) or ROM

鈥?Up to 2.5K Words x 16 Bits of

Data/Program RAM

鈥?544 Words of Dual-Access (DARAM)

鈥?2K Words of Single-Access (SARAM)

Boot ROM (鈥橪F240x Devices)

鈥?SCI/SPI Flash Bootloader

Two Event-Manager (EV) Modules (A and B)

EVA and EVB Each Include:

鈥?Two 16-Bit General-Purpose Timers

鈥?Eight 16-Bit Pulse-Width Modulation

(PWM) Channels Which Enable:

鈥?Three-Phase Inverter Control

鈥?Centered or Edge Alignment of PWM

Channels

鈥?Emergency PWM Channel Shutdown

With External PDPINT Pin

鈥?Programmable Deadband Prevents

Shoot-Through Faults

鈥?Three Capture Units For Time-Stamping

of External Events

鈥?On-Chip Position Encoder Interface

Circuitry

鈥?Synchronized Analog-to-Digital

Conversion

鈥?Suitable for AC Induction, BLDC,

Switched Reluctance, and Stepper Motor

Control

鈥?Applicable for Multiple Motor and/or

Converter Control

External Memory Interface (鈥橪F2407)

鈥?192K Words x 16 Bits of Total Memory,

64K Program, 64K Data, 64K I/O

Watchdog (WD) Timer Module

10-Bit Analog-to-Digital Converter (ADC)

鈥?8 or 16 Multiplexed Input Channels

鈥?500 ns Minimum Conversion Time

鈥?Selectable Twin 8-Input Sequencers

Triggered by Two Event Managers

Controller Area Network (CAN) 2.0B Module

Serial Communications Interface (SCI)

16-Bit Serial Peripheral Interface (SPI)

Module (Except 鈥檟2402)

Phase-Locked-Loop (PLL)-Based Clock

Generation

Up to 40 Individually Programmable,

Multiplexed General-Purpose Input / Output

(GPIO) Pins

Five External Interrupts (Power Drive

Protection, Reset, and Two Maskable

Interrupts)

Power Management:

鈥?Three Power-Down Modes

鈥?Ability to Power-Down Each Peripheral

Independently

Real-Time JTAG-Compliant Scan-Based

Emulation, IEEE Standard 1149.1

鈥?/div>

(JTAG)

Development Tools Include:

鈥?Texas Instruments (TI鈩? ANSI

C Compiler, Assembler / Linker, and

Code Composer鈩?Debugger

鈥?Evaluation Modules

鈥?Scan-Based Self-Emulation (XDS510鈩?

鈥?Numerous Third-Party Digital Motor

Control Support

Package Options

鈥?144-Pin Thin Quad Flatpack (TQFP) PGE

(鈥橪F2407)

鈥?100-Pin TQFP PZ (鈥橪C2404, 鈥橪C2406,

鈥橪F2406)

鈥?64-Pin PQFP PG (鈥橪C2402 and 鈥橪F2402)

Extended Temperature Options (A and S)

鈥?A: 鈥?40擄C to 85擄C

鈥?S: 鈥?40擄C to 125擄C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI, Code Composer, and XDS510 are trademarks of Texas Instruments Incorporated.

鈥?Throughout this data sheet, 鈥?40x is used as a generic name for the 鈥橪F240x/鈥橪C240x family of devices.

鈥?IEEE Standard 1149.1鈥?990, IEEE Standard Test-Access Port

ADVANCE INFORMATION concerns new products in the sampling or

preproduction phase of development. Characteristic data and other

specifications are subject to change without notice.

漏

1999, Texas Instruments Incorporated

POST OFFICE BOX 1443

鈥?/div>

HOUSTON, TEXAS 77251鈥?443

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