TMS320DM642 Datasheet

IC型號(hào)：
TMS320DM642
PDF描述：
Video/Imaging Fixed-Point Digital Signal Processor
文件大小：
1669.24KB
PDF頁(yè)數(shù)：
178頁(yè)
芯片廠家：
TI

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www.ti.com

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200J 鈥?JULY 2002 鈥?REVISED AUGUST 2005

1.1

鈥?/div>

TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor

Features

鈥?/div>

Memory Space

Enhanced Direct-Memory-Access (EDMA)

Controller (64 Independent Channels)

10/100 Mb/s Ethernet MAC (EMAC)

鈥?IEEE 802.3 Compliant

鈥?Media Independent Interface (MII)

鈥?8 Independent Transmit (TX) Channels and

1 Receive (RX) Channel

Management Data Input/Output (MDIO)

Three Configurable Video Ports

鈥?Providing a Glueless I/F to Common Video

Decoder and Encoder Devices

鈥?Supports Multiple Resolutions/Video Stds

VCXO Interpolated Control Port (VIC)

鈥?Supports Audio/Video Synchronization

Host-Port Interface (HPI) [32-/16-Bit]

32-Bit/66-MHz, 3.3-V Peripheral Component

Interconnect (PCI) Master/Slave Interface

Conforms to PCI Specification 2.2

Multichannel Audio Serial Port (McASP)

鈥?Eight Serial Data Pins

鈥?Wide Variety of I

S and Similar Bit Stream

Format

鈥?Integrated Digital Audio I/F Transmitter

Supports S/PDIF, IEC60958-1, AES-3,

CP-430 Formats

Inter-Integrated Circuit (I

C Bus鈩?

Two Multichannel Buffered Serial Ports

Three 32-Bit General-Purpose Timers

Sixteen General-Purpose I/O (GPIO) Pins

Flexible PLL Clock Generator

IEEE-1149.1 (JTAG) Boundary-

Scan-Compatible

548-Pin Ball Grid Array (BGA) Package

(GDK and ZDK Suffixes), 0.8-mm Ball Pitch

548-Pin Ball Grid Array (BGA) Package

(GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch

0.13-碌m/6-Level Cu Metal Process (CMOS)

3.3-V I/O, 1.2-V Internal (-500)

3.3-V I/O, 1.4-V Internal (A-500, A-600, -600,

-720)

鈥?/div>

High-Performance Digital Media Processor

鈥?2-, 1.67-, 1.39-ns Instruction Cycle Time

鈥?500-, 600-, 720-MHz Clock Rate

鈥?Eight 32-Bit Instructions/Cycle

鈥?4000, 4800, 5760 MIPS

鈥?Fully Software-Compatible With C64x鈩?/div>

VelociTI.2鈩?Extensions to VelociTI鈩?/div>

Advanced Very-Long-Instruction-Word (VLIW)

TMS320C64x鈩?DSP Core

鈥?Eight Highly Independent Functional Units

With VelociTI.2鈩?Extensions:

鈥?/div>

Six ALUs (32-/40-Bit), Each Supports

Single 32-Bit, Dual 16-Bit, or Quad 8-Bit

Arithmetic per Clock Cycle

鈥?/div>

Two Multipliers Support Four 16 x 16-Bit

Multiplies (32-Bit Results) per Clock

Cycle or Eight 8 x 8-Bit Multiplies (16-Bit

Results) per Clock Cycle

鈥?Load-Store Architecture With Non-Aligned

Support

鈥?64 32-Bit General-Purpose Registers

鈥?Instruction Packing Reduces Code Size

鈥?All Instructions Conditional

Instruction Set Features

鈥?Byte-Addressable (8-/16-/32-/64-Bit Data)

鈥?8-Bit Overflow Protection

鈥?Bit-Field Extract, Set, Clear

鈥?Normalization, Saturation, Bit-Counting

鈥?VelociTI.2鈩?Increased Orthogonality

L1/L2 Memory Architecture

鈥?128K-Bit (16K-Byte) L1P Program Cache

(Direct Mapped)

鈥?128K-Bit (16K-Byte) L1D Data Cache (2-Way

Set-Associative)

鈥?2M-Bit (256K-Byte) L2 Unified Mapped

RAM/Cache (Flexible RAM/Cache

Allocation)

Endianess: Little Endian, Big Endian

64-Bit External Memory Interface (EMIF)

鈥?Glueless Interface to Asynchronous

Memories (SRAM and EPROM) and

Synchronous Memories (SDRAM, SBSRAM,

ZBT SRAM, and FIFO)

鈥?/div>

1024M-Byte Total Addressable External

鈥?/div>

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this document.

Windows is a registered trademark of Microsoft Corporation.

C Bus is a trademark of Philips Electronics N.V..

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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