TMS320C6747ZKB2 Datasheet

IC型號(hào)：
TMS320C6747ZKB2
PDF描述：
Floating-point Digital Signal Processor
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TMS320C6745/6747 Floating-point Digital Signal Processor

www.ti.com

SPRS377A 鈥?SEPTEMBER 2008 鈥?REVISED OCTOBER 2008

1 TMS320C6745/6747 Floating-point Digital Signal Processor

1.1 Features

鈥?/div>

Applications

鈥?Industrial Control

鈥?USB, Networking

鈥?High-Speed Encoding

鈥?Professional Audio

Software Support

鈥?TI DSP/BIOS鈩?/div>

鈥?Chip Support Library and DSP Library

300-MHz C674x鈩?VLIW DSP

C674x Instruction Set Features

鈥?Superset of the C67x+鈩?and C64x+鈩?ISAs

鈥?2400/1800 C674x MIPS/MFLOPS

鈥?Byte-Addressable (8-/16-/32-/64-Bit Data)

鈥?8-Bit Overflow Protection

鈥?Bit-Field Extract, Set, Clear

鈥?Normalization, Saturation, Bit-Counting

鈥?Compact 16-Bit Instructions

C674x Two Level Cache Memory Architecture

鈥?32K-Byte L1P Program RAM/Cache

鈥?32K-Byte L1D Data RAM/Cache

鈥?256K-Byte L2 Unified Mapped RAM/Cache

鈥?Flexible RAM/Cache Partition (L1 and L2)

鈥?1024K-Byte L2 ROM

Enhanced Direct-Memory-Access Controller 3

(EDMA3):

鈥?2 Transfer Controllers

鈥?32 Independent DMA Channels

鈥?8 Quick DMA Channels

鈥?Programmable Transfer Burst Size

TMS320C674x鈩?Floating Point VLIW DSP Core

鈥?Load-Store Architecture With Non-Aligned

Support

鈥?64 General-Purpose Registers (32 Bit)

鈥?Six ALU (32-/40-Bit) Functional Units

鈥?/div>

Supports 32-Bit Integer, SP (IEEE Single

Precision/32-Bit) and DP (IEEE Double

Precision/64-Bit) Floating Point

鈥?/div>

Supports up to Four SP Additions Per

Clock, Four DP Additions Every 2

Clocks

鈥?/div>

Supports up to Two Floating Point (SP

or DP) Approximate Reciprocal or

Square Root Operations Per Cycle

鈥?Two Multiply Functional Units

Mixed-Precision IEEE Floating Point

Multiply Supported up to:

鈥?2 SP x SP -> SP Per Clock

鈥?2 SP x SP -> DP Every Two Clocks

鈥?2 SP x DP -> DP Every Three Clocks

鈥?2 DP x DP -> DP Every Four Clocks

鈥?/div>

Fixed Point Multiply Supports Two 32 x

32-Bit Multiplies, Four 16 x 16-Bit

Multiplies, or Eight 8 x 8-Bit Multiplies

per Clock Cycle, and Complex Multiples

鈥?Instruction Packing Reduces Code Size

鈥?All Instructions Conditional

鈥?Hardware Support for Modulo Loop

Operation

鈥?Protected Mode Operation

鈥?Exceptions Support for Error Detection and

Program Redirection

128K-Byte RAM Shared Memory

Two External Memory Interfaces:

鈥?EMIFA

鈥?/div>

NOR (8-/16-Bit-Wide Data)

鈥?/div>

NAND (8-/16-Bit-Wide Data)

鈥?/div>

16-Bit SDRAM With 128MB Address

Space

鈥?EMIFB

鈥?/div>

32-Bit or 16-Bit SDRAM With 256MB

Address Space

Three Configurable 16550 type UART Modules:

鈥?UART0 With Modem Control Signals

鈥?16-byte FIFO

鈥?16x or 13x Oversampling Option

LCD Controller

Two Serial Peripheral Interfaces (SPI) Each

With One Chip-Select

Multimedia Card (MMC)/Secure Digital (SD)

Card Interface with Secure Data I/O (SDIO)

Two Master/Slave Inter-Integrated Circuit (I

Bus鈩?

USB 1.1 OHCI (Host) With Integrated PHY

(USB1)

USB 2.0 OTG Port With Integrated PHY (USB0)

鈥?USB 2.0 High-/Full-Speed Client

鈥?USB 2.0 High-/Full-/Low-Speed Host

鈥?End Point 0 (Control)

鈥?/div>

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this document.

C674x, TMS320C6000, C6000 are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the

formative or design phase of development. Characteristic data and

other specifications are design goals. Texas Instruments reserves

the right to change or discontinue these products without notice.

PRODUCT PREVIEW

鈥?/div>

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