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TMS320C6712 Datasheet

  • TMS320C6712

  • FLOATING-POINT DIGITAL SIGNAL PROCESSORS

  • 1612.04KB

  • 110頁(yè)

  • TI

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TMS320C6712, TMS320C6712C, TMS320C6712D
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS148J
鈭?/div>
AUGUST 2000
鈭?/div>
REVISED MAY 2004
D
Low-Price/High-Performance Floating-Point
Digital Signal Processors (DSPs):
TMS320C67x錚?(TMS320C6712, C6712C,
C6712D)
鈭?/div>
Eight 32-Bit Instructions/Cycle
鈭?/div>
100-, 150-MHz Clock Rates
鈭?/div>
10-, 6.7-ns Instruction Cycle Times
鈭?/div>
600, 900 MFLOPS
Advanced Very Long Instruction Word
(VLIW) C67x錚?DSP Core
鈭?/div>
Eight Highly Independent Functional
Units:
鈭?/div>
Four ALUs (Floating- and Fixed-Point)
鈭?/div>
Two ALUs (Fixed-Point)
鈭?/div>
Two Multipliers (Floating- and
Fixed-Point)
鈭?/div>
Load-Store Architecture With 32 32-Bit
General-Purpose Registers
鈭?/div>
Instruction Packing Reduces Code Size
鈭?/div>
All Instructions Conditional
Instruction Set Features
鈭?/div>
Hardware Support for IEEE
Single-Precision and Double-Precision
Instructions
鈭?/div>
Byte-Addressable (8-, 16-, 32-Bit Data)
鈭?/div>
8-Bit Overflow Protection
鈭?/div>
Saturation
鈭?/div>
Bit-Field Extract, Set, Clear
鈭?/div>
Bit-Counting
鈭?/div>
Normalization
L1/L2 Memory Architecture
鈭?/div>
32K-Bit (4K-Byte) L1P Program Cache
(Direct Mapped)
鈭?/div>
32K-Bit (4K-Byte) L1D Data Cache
(2-Way Set-Associative)
鈭?/div>
512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible Data/Program Allocation)
Device Configuration
鈭?/div>
Boot Mode: 8- and 16-Bit ROM Boot
鈭?/div>
Endianness: Little Endian (12/12C)
Little Endian, Big Endian (12D)
Enhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
D
16-Bit External Memory Interface (EMIF)
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
鈭?/div>
Glueless Interface to Asynchronous
Memories: SRAM and EPROM
鈭?/div>
Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
鈭?/div>
256M-Byte Total Addressable External
Memory Space
Two Multichannel Buffered Serial Ports
(McBSPs)
鈭?/div>
Direct Interface to T1/E1, MVIP, SCSA
Framers
鈭?/div>
ST-Bus-Switching Compatible
鈭?/div>
Up to 256 Channels Each
鈭?/div>
AC97-Compatible
鈭?/div>
Serial-Peripheral-Interface (SPI)
Compatible (Motorola錚?
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked-Loop (PLL) Clock
Generator [C6712]
Flexible Software-Configurable PLL-Based
Clock Generator Module [C6712C/C6712D]
A Dedicated General-Purpose Input/Output
(GPIO) Module With 5 Pins [12C/12D]
IEEE-1149.1 (JTAG
鈥?/div>
)
Boundary-Scan-Compatible
256-Pin Ball Grid Array (BGA) Package
(GFN Suffix) [C6712 Only]
272-Pin Ball Grid Array (BGA) Package
(GDP Suffix) [C6712C/C6712D Only]
CMOS Technology
鈭?/div>
0.13-碌m/6-Level Copper Metal Process
(C6712C/C6712D)
鈭?/div>
0.18-碌m/5-Level Metal Process (C6712)
3.3-V I/Os, 1.20
鈥?/div>
-V Internal
(C6712C/C6712D)
3.3-V I/Os, 1.8-V Internal (C6712)
D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C67x and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
Other trademarks are the property of their respective owners.
鈥?/div>
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
鈥?/div>
These values are compatible with existing 1.26V designs.
This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
Copyright
錚?/div>
2004, Texas Instruments Incorporated
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈭?443
1

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