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TMS320C6455BZTZ2 Datasheet

  • TMS320C6455BZTZ2

  • Fixed-Point Digital Signal Processor

  • 250頁

  • TI

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TMS320C6455
Fixed-Point Digital Signal Processor
SPRS276H 鈥?MAY 2005 鈥?REVISED OCTOBER 2007
1 Features
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High-Performance Fixed-Point DSP (C6455)
鈥?1.39-, 1.17, 1-, and 0.83-ns Instruction Cycle
Time
鈥?720-MHz, 850-MHz, 1-GHz, and 1.2-GHz
Clock Rate
鈥?Eight 32-Bit Instructions/Cycle
鈥?9600 MIPS/MMACS (16-Bits)
鈥?Commercial Temperature [0擄C to 90擄C]
鈥?Extended Temperature [-40擄C to 105擄C]
TMS320C64x+鈩?DSP Core
鈥?Dedicated SPLOOP Instruction
鈥?Compact Instructions (16-Bit)
鈥?Instruction Set Enhancements
鈥?Exception Handling
TMS320C64x+ Megamodule L1/L2 Memory
Architecture:
鈥?256K-Bit (32K-Byte) L1P Program Cache
[Direct Mapped]
鈥?256K-Bit (32K-Byte) L1D Data Cache
[2-Way Set-Associative]
鈥?16M-Bit (2096K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
鈥?256K-Bit (32K-Byte) L2 ROM
鈥?Time Stamp Counter
Enhanced VCP2
鈥?Supports Over 694 7.95-Kbps AMR
鈥?Programmable Code Parameters
Enhanced Turbo Decoder Coprocessor (TCP2)
鈥?Supports up to Eight 2-Mbps 3GPP
(6 Iterations)
鈥?Programmable Turbo Code and Decoding
Parameters
Endianess: Little Endian, Big Endian
64-Bit External Memory Interface (EMIFA)
鈥?Glueless Interface to Asynchronous
Memories (SRAM, Flash, and EEPROM) and
Synchronous Memories (SBSRAM, ZBT
SRAM)
鈥?Supports Interface to Standard Sync
Devices and Custom Logic (FPGA, CPLD,
ASICs, etc.)
鈥?32M-Byte Total Addressable External
Memory Space
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Four 1x Serial RapidIO廬 Links (or One 4x),
v1.2 Compliant
鈥?1.25-, 2.5-, 3.125-Gbps Link Rates
鈥?Message Passing, DirectIO Support, Error
Management Extensions, and Congestion
Control
鈥?IEEE 1149.6 Compliant I/Os
DDR2 Memory Controller
鈥?Interfaces to DDR2-533 SDRAM
鈥?32-Bit/16-Bit, 533-MHz (data rate) Bus
鈥?512M-Byte Total Addressable External
Memory Space
EDMA3 Controller (64 Independent Channels)
32-/16-Bit Host-Port Interface (HPI)
32-Bit 33-/66-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to
PCI Local Bus Specification
(version 2.3)
One Inter-Integrated Circuit (I
2
C) Bus
Two McBSPs
10/100/1000 Mb/s Ethernet MAC (EMAC)
鈥?IEEE 802.3 Compliant
鈥?Supports Multiple Media Independent
Interfaces (MII, GMII, RMII, and RGMII)
鈥?8 Independent Transmit (TX) and
8 Independent Receive (RX) Channels
Two 64-Bit General-Purpose Timers,
Configurable as Four 32-Bit Timers
UTOPIA
鈥?UTOPIA Level 2 Slave ATM Controller
鈥?8-Bit Transmit and Receive Operations up
to 50 MHz per Direction
鈥?User-Defined Cell Format up to 64 Bytes
16 General-Purpose I/O (GPIO) Pins
System PLL and PLL Controller
Secondary PLL and PLL Controller, Dedicated
to EMAC and DDR2 Memory Controller
Advanced Event Triggering (AET) Compatible
Trace-Enabled Device
IEEE-1149.1 (JTAG鈩?
Boundary-Scan-Compatible
697-Pin Ball Grid Array (BGA) Package
(ZTZ or GTZ Suffix), 0.8-mm Ball Pitch
0.09-渭m/7-Level Cu Metal Process (CMOS)
3.3-/1.8-/1.5-/1.25-/1.2-V I/Os, 1.25-/1.2-V
Internal
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All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 漏 2005鈥?007, Texas Instruments Incorporated

TMS320C6455BZTZ2 產(chǎn)品屬性

  • 1

  • 集成電路 (IC)

  • 嵌入式 - DSP（數(shù)字式信號處理器）

  • TMS320C645x

  • 定點

  • 主機接口，I²C，McBSP，PCI，UTOPIA

  • 1.2GHz

  • ROM（32 kB）

  • 2.1MB

  • 1.2V，1.25V，1.5V，1.8V，3.3V

  • 1.20V

  • 0°C ~ 90°C

  • 表面貼裝

  • 697-BFBGA，F(xiàn)CBGA

  • 697-FCBGA（24x24）

  • 托盤

  • TMDXEVM6452-ND - TMDXEVM6452296-23036-ND - DSP STARTER KIT FOR TMDS320C6455

  • 296-26842-5TMS320C6455BZTZ2-ND

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