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TMS320C6421 Datasheet

  • TMS320C6421

  • Fixed-Point Digital Signal Processor

  • 563.53KB

  • 59頁

  • TI

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TMS320C6421
Fixed-Point Digital Signal Processor
SPRS346A 鈥?JANUARY 2007 鈥?REVISED MARCH 2007
1 TMS320C6421 Fixed-Point Digital Signal Processor
1.1 Features
鈥?/div>
High-Performance Digital Signal Processor
(C6421)
鈥?2.5-, 2.-, 1.67-ns Instruction Cycle Time
鈥?400-, 500-, 600-MHz C64x+鈩?Clock Rate
鈥?Eight 32-Bit C64x+ Instructions/Cycle
鈥?3200, 4000, 4800 MIPS
鈥?Fully Software-Compatible With C64x
鈥?Commercial and Extended Temperature
Ranges
VelociTI.2鈩?Extensions to VelociTI鈩?/div>
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+鈩?DSP Core
鈥?Eight Highly Independent Functional Units
With VelociTI.2 Extensions:
鈥?/div>
Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
鈥?/div>
Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
鈥?Load-Store Architecture With Non-Aligned
Support
鈥?64 32-Bit General-Purpose Registers
鈥?Instruction Packing Reduces Code Size
鈥?All Instructions Conditional
鈥?Additional C64x+鈩?Enhancements
鈥?/div>
Protected Mode Operation
鈥?/div>
Exceptions Support for Error Detection
and Program Redirection
鈥?/div>
Hardware Support for Modulo Loop
Auto-Focus Module Operation
C64x+ Instruction Set Features
鈥?Byte-Addressable (8-/16-/32-/64-Bit Data)
鈥?8-Bit Overflow Protection
鈥?Bit-Field Extract, Set, Clear
鈥?Normalization, Saturation, Bit-Counting
鈥?VelociTI.2 Increased Orthogonality
鈥?C64x+ Extensions
鈥?/div>
Compact 16-bit Instructions
鈥?/div>
Additional Instructions to Support
Complex Multiplies
C64x+ L1/L2 Memory Architecture
鈥?128K-Bit (16K-Byte) L1P Program
RAM/Cache [Flexible Allocation]
鈥?128K-Bit (16K-Byte) L1D Data RAM/Cache
[Flexible Allocation]
鈥?512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
Endianess: Supports Both Little Endian and
Big Endian
External Memory Interfaces (EMIFs)
鈥?16-Bit DDR2 SDRAM Memory Controller
With 128M-Byte Address Space (1.8-V I/O)
鈥?Asynchronous 8-Bit-Wide EMIF (EMIFA)
With up to 64M-Byte Address Reach
鈥?/div>
Flash Memory Interfaces
鈥?/div>
NOR (8-Bit-Wide Data)
鈥?/div>
NAND (8-Bit-Wide Data)
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
Two 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
One 64-Bit Watch Dog Timer
One UART With RTS and CTS Flow Control
Master/Slave Inter-Integrated Circuit
(I
2
C Bus鈩?
Multichannel Buffered Serial Port (McBSP0)
鈥?I2S and TDM
鈥?AC97 Audio Codec Interface
鈥?SPI
鈥?Standard Voice Codec Interface (AIC12)
鈥?Telecom Interfaces 鈥?ST-Bus, H-100
鈥?128 Channel Mode
Multichannel Audio Serial Port (McASP0)
鈥?Four Serializers and SPDIF (DIT) Mode
16-Bit Host-Port Interface (HPI)
10/100 Mb/s Ethernet MAC (EMAC)
鈥?IEEE 802.3 Compliant
鈥?Supports Multiple Media Independent
Interfaces (MII, RMII)
鈥?Management Data I/O (MDIO) Module
VLYNQ鈩?Interface (FPGA Interface)
Three Pulse Width Modulator (PWM) Outputs
On-Chip ROM Bootloader
Individual Power-Savings Modes
Flexible PLL Clock Generators
IEEE-1149.1 (JTAG鈩?
Boundary-Scan-Compatible
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
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鈥?/div>
鈥?/div>
鈥?/div>
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鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright 漏 2007鈥?007, Texas Instruments Incorporated
PRODUCT PREVIEW
鈥?/div>

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