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(JTAG) Boundary Scan
Logic
8.5-ns Single-Cycle Fixed-Point Instruction
Execution Time (117.96 MIPS) or 17-ns
Instruction Execution Time (58.98 MIPS) for
3.3-V Power Supply (1.5-V Core)
Available in a 144-Pin Plastic Low-Profile
Quad Flatpack (LQFP) (PGE Suffix) and a
144-Pin Ball Grid Array (BGA) (GGU Suffix)
description
The TMS320C54V90 is used to implement a full-featured, high-performance modem technology, intended for
use in embedded systems and similar applications. This highly integrated solution implements a complete
modem using only two chips: the TMS320C54V90 DSP with on-chip RAM and ROM, and the Si3016 line-side
DAA.
The modem can connect to a host system serially (RS-232 functionality), or as an 8-bit peripheral to the
processor in a host system. The TMS320C54V90 uses a standard Digital Signal Processor (DSP) and
proprietary firmware to perform all the modem signal processing, the V.42/V.42bis compression, and AT
commands interpretation for modem control functions.
.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Note:
Human Body Model ESD test performance for this product was demonstrated to be
鹵1.5
kV during product qualification. Industry standard
test method used was IEA/JESD22-A114. Adherence to ESD handling precautionary procedures is advised at all times.
All trademarks are the property of their respective owners.
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IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright
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2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443
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HOUSTON, TEXAS 77251鈭?443
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