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THS5641AIDW Datasheet

  • THS5641AIDW

  • 8-BIT, 100 MSPS, CommsDACE DIGITAL-TO-ANALOG CONVERTER

  • 704.71KB

  • 28頁

  • TI

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THS5641A
8-BIT, 100 MSPS, CommsDAC鈩?/div>
DIGITAL-TO-ANALOG CONVERTER
SLAS277 鈥揗ARCH 2000
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Member of the Pin-Compatible
CommsDAC鈩?Product Family
100 MSPS Update Rate
8-Bit Resolution
Signal-to-Noise and Distortion Ratio
(SINAD) at 5 MHz: 50 dB
Integral Nonlinearity INL: 0.25 LSB
Differential Nonlinearity DNL: 0.25 LSB
1 ns Setup/Hold Time
Glitch Energy: 5 pV-s
Settling Time to 0.1%: 35 ns
Differential Scalable Current Outputs: 2 mA
to 20 mA
On-Chip 1.2-V Reference
3-V and 5-V Single Supply Operation
Straight Binary or Twos Complement Input
Power Dissipation: 100 mW at 3.3 V, Sleep
Mode: 17 mW at 3.3 V
Package: 28-Pin SOIC and TSSOP
SOIC (DW) OR TSSOP (PW) PACKAGE
(TOP VIEW)
D7
D6
D5
D4
D3
D2
D1
D0
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLK
DV
DD
DGND
MODE
AV
DD
COMP2
IOUT1
IOUT2
AGND
COMP1
BIASJ
EXTIO
EXTLO
SLEEP
NC 鈥?No internal connection
description
The THS5641A is an 8-bit resolution digital-to-analog converter (DAC) optimized for video applications and
digital data transmission in wired and wireless communication systems. The 8-bit DAC is a member of the
CommsDAC鈩?series of high-speed, low-power CMOS digital-to-analog converters. The CommsDAC鈩?family
consists of pin compatible 14-, 12-, 10-, and 8-bit DACs. All devices offer identical interface options, small outline
package and pinout. The THS5641A offers superior ac and dc performance while supporting update rates up
to 100 MSPS.
The THS5641A operates from an analog and digital supply of 3 V to 5.5 V. Its inherent low power dissipation
of 100 mW ensures that the device is well suited for portable and low power applications. Lowering the full-scale
current output reduces the power dissipation without significantly degrading performance. The device features
a SLEEP mode, which reduces the standby power to approximately 17 mW, thereby optimizing the power
consumption for system needs.
The THS5641A is manufactured in Texas Instruments advanced high-speed mixed-signal CMOS process. A
current-source-array architecture combined with simultaneous switching shows excellent dynamic
performance. On-chip edge-triggered input latches and a 1.2 V temperature compensated bandgap reference
provide a complete monolithic DAC solution. The digital supply range of 3 V to 5.5 V supports 3 V and 5 V CMOS
logic families. Minimum data input setup and hold times allow for easy interfacing with external logic. The
THS5641A supports both a straight binary and twos complement input word format, enabling flexible interfacing
with digital signal processors.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CommsDAC is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
2000, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

THS5641AIDW 產(chǎn)品屬性

  • Data Converter Basics

  • 20

  • 集成電路 (IC)

  • 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器

  • CommsDAC™

  • 35ns

  • 8

  • 并聯(lián)

  • 1

  • 單電源

  • 175mW

  • -40°C ~ 85°C

  • 表面貼裝

  • 28-SOIC（0.295"，7.50mm 寬）

  • 28-SOIC

  • 管件

  • 2 電流，單極

  • 100M

  • 296-10055-ND - EVAL MOD FOR THS5641

  • 296-2989-5

THS5641AIDW相關(guān)型號PDF文件下載

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