鈥?/div>
7
CMOS pipelined analog-to-digital converter. A
29
V
REFIN
+
8
differential sample and hold minimizes even order
28
harmonics and allows for a high degree of
V
REFOUT
+
9
27
V
BG 10
common mode rejection at the analog input. A
26
AV
SS 11
buffered analog input enables operation with a
25
AV
DD 12
constant analog input impedance, and prevents
transient voltage spikes from feeding backward to
13 14 15 16 17 18 19 20 21 22 23 24
the analog input source. Full temperature DNL
performance allows for industrial application with
the assurance of no missing codes. The typical
integral nonlinearity (INL) for the THS1050 is less
than one LSB. The superior INL curve of the THS1050 results in SFDR performance that is exceptional for a
10-bit analog-to-digital converter. The THS1050 can operate with either internal or external references. Internal
reference usage selection is accomplished simply by externally connecting reference output terminals to
reference input terminals.
AVAILABLE OPTIONS
PACKAGE
TA
鈥?40擄C to 85擄C
0擄C to 70擄C
48-TQFP
(PHP)
THS1050I
THS1050C
NC
NC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
漏
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
DVSS
CLK+
CLK鈥?/div>
DVDD
DVSS
DVSS
DVDD
DVSS
DVDD
DRVSS
DRVDD
AV SS
1
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