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THS10064CDA Datasheet

  • THS10064CDA

  • 10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVE...

  • 41頁

  • TI

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THS10064
10-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER
SLAS255 鈥?DECEMBER 1999
features
applications
D
D
D
D
D
D
D
D
D
D
D
Simultaneous Sampling of 4 Single-Ended
Signals or 2 Differential Signals or
Combination of Both
Integrated 16-Word FIFO
Signal-to-Noise and Distortion Ratio: 59 dB
at f
I
= 2 MHz
Differential Nonlinearity Error:
鹵1
LSB
Integral Nonlinearity Error:
鹵1
LSB
Auto-Scan Mode for 2, 3, or 4 Inputs
3-V or 5-V Digital Interface Compatible
Low Power: 216 mW Max
5-V Analog Single Supply Operation
Internal Voltage References . . . 50 PPM/擄C
and
鹵5%
Accuracy
Parallel
碌C/DSP
Interface
D
D
D
D
D
Radar Applications
Communications
Control Applications
High-Speed DSP Front-End
Automotive Applications
DA (TSSOP) PACKAGE
(TOP VIEW)
D0
D1
D2
D3
D4
D5
BV
DD
BGND
D6
D7
D8
D9
RA0
RA1
CONV_CLK (CONVST)
DATA_AV
1
2
3
4
5
6
7
8
9
10
32
31
30
29
28
27
26
25
24
23
description
The THS10064 is a CMOS, low-power, 10-bit,
11
22
6 MSPS analog-to-digital converter (ADC). The
12
21
speed, resolution, bandwidth, and single-supply
13
20
operation are suited for applications in radar,
14
19
imaging,
high-speed
acquisition,
and
15
18
communications.
A
multistage
pipelined
16
17
architecture with output error correction logic
provides for no missing codes over the full
operating temperature range. Internal control
registers are used to program the ADC into the desired mode. The THS10064 consists of four analog inputs,
which are sampled simultaneously. These inputs can be selected individually and configured to single-ended
or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to improve data
transfers to the processor. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided.
An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the
application. Two different conversion modes can be selected. In single conversion mode, a single and
simultaneous conversion of up to four inputs can be initiated by using the single conversion start signal
(CONVST). The conversion clock in single conversion mode is generated internally using a clock oscillator
circuit. In continuous conversion mode, an external clock signal is applied to the CONV_CLK input of the
THS10064. The internal clock oscillator is switched off in continuous conversion mode.
The THS10064C is characterized for operation from 0擄C to 70擄C, and the THS10064I is characterized for
operation from 鈥?0擄C to 85擄C.
AINP
AINM
BINP
BINM
REFIN
REFOUT
REFP
REFM
AGND
AV
DD
CS0
CS1
WR (R/W)
RD
DV
DD
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1999, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

THS10064CDA 產(chǎn)品屬性

  • Data Converter Basics

  • 46

  • 集成電路 (IC)

  • 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器

  • -

  • 10

  • 6M

  • 并聯(lián)

  • 1

  • 216mW

  • 模擬和數(shù)字

  • 0°C ~ 70°C

  • 表面貼裝

  • 32-TSSOP（0.240"，6.10mm 寬）

  • 32-TSSOP

  • 管件

  • 4 個單端，單極；2 個差分，單極

  • 296-2172-5

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