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TFP501 Datasheet

  • TFP501

  • PANELBUS HDCP DIGITAL RECEIVER

  • 24頁

  • TI

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TFP501
PanelBus錚?/div>
HDCP DIGITAL RECEIVER
SLDS127B 鈥?JULY 2001 鈥?REVISED AUGUST 2002
D
Supports UXGA Resolution (Output Pixel
D
D
D
D
D
Rates up to 165 MHz)
Digital Visual Interface (DVI) and
High-Bandwidth Digital Content Protection
(HDCP) Specification Compliant
1
Encrypted External HDCP Device Key
Storage for Exceptional Security and Ease
of Implementation
True-Color, 24 Bits/Pixel, 48-bit Dual Pixel
Output Mode, 16.7M Colors at 1 or 2 Pixels
Per Clock
Laser Trimmed (50-鈩? Input Stage for
Optimum Fixed Impedance Matching
Skew Tolerant up to One Pixel Clock Cycle
(High Clock and Data Jitter Tolerance)
D
4x Over-Sampling for Reduced Bit-Error
D
D
D
D
D
Rates and Better Performance Over Longer
Cables
Reduced Power Consumption From 1.8-V
Core Operation With 3.3-V I/O鈥檚 and
Supplies
2
Reduced Ground-Bounce Using Time
Staggered Pixel Outputs
Lowest Noise and Best Power Dissipation
Using TI 100-pin TQFP PowerPAD錚?/div>
Packaging
Advanced Technology Using TI鈥檚 0.18-碌m
EPIC-5錚?CMOS Process
Supports Hot Plug Detection
description
The TFP501 is a Texas Instruments
PanelBus
flat panel display product, part of a comprehensive family of
end-to-end DVI 1.0-compliant solutions. Targeted primarily at desktop LCD monitors, DLP and LCD projectors,
and digital TVs, the TFP501 finds applications in any design requiring high-speed digital interface with the
additional benefit of an extremely robust and innovative encryption scheme for digital content protection.
The TFP501 supports display resolutions up to UXGA, including the standard HDTV formats, in 24-bit true color
pixel format. The TFP501 offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN
panels, and provides an option for time staggered pixel outputs for reduced ground-bounce.
PowerPAD advanced packaging technology results in best-of-class power dissipation, footprint, and ultra-low
ground inductance.
The TFP501 combines
PanelBus
circuit innovation and unique implementation for HDCP key protection with
TI鈥檚 advanced 0.18
碌m
EPIC-5 CMOS process technology to achieve a completely secure, reliable,
low-powered, low noise, high-speed digital interface solution.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Footnotes:
1.
The digital visual interface (DVI) specification is an industry standard developed by the digital display working group (DDWG) for high鈥搒peed
digital connection to digital displays. The high鈥揵andwidth digital content protection system (HDCP) is an industry standard for protecting
DVI outputs from being copied. HDCP was developed by Intel Corporation and is licensed by the Digital Content Protection, LLC. The
TFP501 is compliant to the DVI Rev. 1.0 and HDCP Rev. 1.0 specifications.
The TFP501 has an internal voltage regulator that provides the 1.8 V core power supply from the externally supplied 3.3 V supplies.
2.
PanelBus,
PowerPAD and EPIC-5 are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
錚?/div>
2002, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

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