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TC59LM836DKG-30 Datasheet

  • TC59LM836DKG-30

  • MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

  • 65頁

  • TOSHIBA

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TC59LM836DKG-30,-33,-40
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
288Mbits Network FCRAM2
鈭?/div>
2,097,152-WORDS
脳
4 BANKS
脳
36-BITS
DESCRIPTION
Lead-Free
Network FCRAM
TM
is Double Data Rate Fast Cycle Random Access Memory. TC59LM836DKG is Network
FCRAM
TM
containing 301,989,888 memory cells. TC59LM836DKG is organized as 2,097,152-words
脳
4 banks
脳
36
bits. TC59LM836DKG feature a fully synchronous operation referenced to clock edge whereby all operations are
synchronized at a clock input which enables high performance and simple user interface coexistence.
TC59LM836DKG can operate fast core cycle compared with regular DDR SDRAM.
TC59LM836DKG is suitable for Network and other applications where large memory density and low power
consumption are required. The Output Driver for Network FCRAM
TM
is capable of high quality fast data transfer
under light loading condition.
FEATURES
PARAMETER
-30
CL
=
4
t
CK
t
RC
t
RAC
Clock Cycle Time (min)
CL
=
5
CL
=
6
Random Read/Write Cycle Time (min)
Random Access Time (max)
4.0 ns
3.5 ns
3.0 ns
20.0 ns
20.0 ns
380 mA
100 mA
15 mA
TC59LM836DKG
-33
4.5 ns
3.75 ns
3.33 ns
22.5 ns
22.5 ns
360 mA
95 mA
15 mA
-40
5.0 ns
4.5 ns
4.0 ns
25 ns
25 ns
340 mA
90 mA
15 mA
I
DD1S
Operating Current (single bank) (max)
l
DD2P
Power Down Current (max)
l
DD6
Self-Refresh Current (max)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Fully Synchronous Operation
鈥?/div>
Double Data Rate (DDR)
Data input/output are synchronized with both edges of DS / QS.
鈥?/div>
Differential Clock (CLK and
CLK
) inputs
CS
, FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and QS) is aligned to the crossings of CLK and
CLK
.
Fast clock cycle time of 3.0 ns minimum
Clock: 333 MHz maximum
Data: 666 Mbps/pin maximum
Quad Independent Banks operation
Fast cycle and Short Latency
Selectable Data Strobe
Distributed Auto-Refresh cycle in 3.9
碌s
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency
=
CAS
Latency-1
Programable
CAS
Latency and Burst Length
CAS
Latency
=
4, 5, 6
Burst Length
=
2, 4
Organization: 2,097,152 words
脳
4 banks
脳
36 bits
Power Supply Voltage
V
DD
:
2.5 V
鹵
0.125V
V
DDQ
: 1.4 V ~ 1.9 V
Low voltage CMOS I/O covered with SSTL_18 (Half strength driver) and HSTL.
JTAG boundary scan
Package: 144Ball BGA, 1mm
脳
0.8mm Ball pitch (P-TFBGA144-1119-0.80BZ)
Lead-Free
Notice: FCRAM is trademark of Fujitsu limited, Japan.
Rev 1.3
2005-03-07
1/65

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