TC55NEM216ASTV55,70
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55NEM216ASTV is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by
16 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.7 to
5.5 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of
3 mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 1
碌A(chǔ)
standby
current (typ) when chip enable (
CE
) is asserted high or chip select (CS) is asserted low. There are three control
inputs.
CE
is used to select the device and for data retention control, and output enable (
OE
) provides fast
memory access. Data byte control pin (
LB ,
UB
) provides lower and upper byte access. This device is well suited to
various microprocessor system applications where high speed, low power and battery backup are required. And,
with a guaranteed operating extreme temperature range of
鈭?/div>
40擄 to 85擄C, the TC55NEM216ASTV can be used in
environments exhibiting extreme temperature conditions. The TC55NEM216ASTV is available in a plastic 44-pin
thin-small-outline package (TSOP).
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Low-power dissipation
Operating: 15 mW/MHz (typical)
Single power supply voltage of 2.7 to 5.5 V
Power down features using
CE
Data retention supply voltage of 2.0 to 5.5 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
鈭?/div>
40擄 to 85擄C
Standby Current (maximum): 20
碌
A
鈥?/div>
Access Times (maximum):
TC55NEM216ASTV
55
Access Time
CE Access Time
OE Access Time
55 ns
55 ns
30 ns
70
70 ns
70 ns
35 ns
鈥?/div>
Package:
TSOP II44-P-400-0.80
(Weight:
g typ)
PIN ASSIGNMENT
(TOP VIEW)
44 PIN TSOP
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
V
DD
GND
I/O5
I/O6
I/O7
I/O8
R/W
A15
A14
A13
A12
A16
PIN NAMES
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
GND
V
DD
I/O12
I/O11
I/O10
I/O9
CS
A8
A9
A10
A11
A17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A0~A17
Address Inputs
CE
CS
R/W
Chip Enable
Chip Select
Read/Write Control
Output Enable
Data Byte Control
Data Inputs/Outputs
Power
Ground
No Connection
OE
LB , UB
I/O1~I/O16
V
DD
GND
NC
2002-10-30
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