TC55NEM216AFTN55,70
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55NEM216AFTN is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by
16 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5V
鹵
10% power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3
mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 1
碌A(chǔ)
standby
current (typ) when chip enable ( CE ) is asserted high. There are two control inputs. CE is used to select the device
and for data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB ,
UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating extreme
temperature range of
鈭?0擄
to 85擄C, the TC55NEM216AFTN can be used in environments exhibiting extreme
temperature conditions. The TC55NEM216AFTN is available in a plastic 54-pin thin-small-outline package
(TSOP).
FEATURES
鈥?/div>
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鈥?/div>
鈥?/div>
鈥?/div>
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Low-power dissipation
Operating: 15 mW/MHz (typical)
Single power supply voltage of 5 V
鹵
10%
Power down features using CE
Data retention supply voltage of 2.0 to 5.5 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
鈭?0擄
to 85擄C
Standby Current (maximum): 20
碌A(chǔ)
鈥?/div>
Access Times (maximum):
TC55NEM216AFTN
55
Access Time
CE
Access Time
OE
Access Time
70
70 ns
70 ns
35 ns
55 ns
55 ns
30 ns
鈥?/div>
Package:
TSOP II54-P-400-0.80
(Weight:
g typ)
PIN ASSIGNMENT
(TOP VIEW)
54 PIN TSOP
NC
A3
A2
A1
A0
I/O16
I/O15
V
DD
GND
I/O14
I/O13
UB
CE
OP
R/W
I/O12
I/O11
GND
V
DD
I/O10
I/O9
NC
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
A4
A5
A6
A7
NC
I/O1
I/O2
V
DD
GND
I/O3
I/O4
LB
OE
OP
NC
I/O5
I/O6
GND
V
DD
I/O7
I/O8
A8
A9
A10
A11
A12
NC
PIN NAMES
A0~A17
CE
Address Inputs
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Data Inputs/Outputs
Power (+5 V)
Ground
No Connection
Option
R/W
OE
LB ,
UB
I/O1~I/O16
V
DD
GND
NC
OP*
*:
OP pin must be open or connected to GND.
2002-07-04
1/11
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