EVALUATION
KIT
AVAILABLE
TC500
TC500A
TC510
TC514
1
PRECISION ANALOG FRONT ENDS
FEATURES
s
s
s
s
s
s
s
s
s
Precision (up to 17 Bits) A/D Converter "Front End"
3-Pin Control Interface to Microprocessor
Flexible: User Can Trade-Off Conversion Speed
for Resolution
Single Supply Operation (TC510/514)
4 Input, Differential Analog MUX (TC514)
Automatic Input Voltage Polarity Detection
Low Power Dissipation ........... TC500/500A: 10mW
TC510/514: 18mW
Wide Analog Input Range .......
鹵
4.2V (TC500A/510)
Directly Accepts Bipolar and Differential Input
Signals
GENERAL DESCRIPTION
The TC500/500A/510/514 family are precision analog
front ends that implement dual slope A/D converters having
a maximum resolution of 17 bits plus sign. As a minimum,
each device contains the integrator, zero crossing compara-
tor and processor interface logic. The TC500 is the base
(16 bit max) device and requires both positive and negative
power supplies. The TC500A is identical to the TC500,
except it has improved linearity allowing it to operate to a
maximum resolution of 17 bits. The TC510 adds an on-
board negative power supply converter for single supply
operation. The TC514 adds both a negative power supply
converter and a 4 input differential analog multiplexer.
Each device has the same processor control interface
consisting of 3 wires: control inputs A and B and zero-
crossing comparator output (CMPTR). The processor ma-
nipulates A, B to sequence the TC5xx through four phases
of conversion: Auto Zero, Integrate, Deintegrate and Inte-
grator Zero. During the Auto Zero phase, offset voltages in
the TC5xx are corrected by a closed-loop feedback mecha-
nism. The input voltage is applied to the integrator during the
Integrate phase. This causes an integrator output dv/dt
directly proportional to the magnitude of the input voltage.
The higher the input voltage, the greater the magnitude of
the voltage stored on the integrator during this phase. At the
start of the Deintegrate phase, an external voltage reference
is applied to the integrator, and at the same time, the external
host processor starts its on-board timer. The processor main-
RINT
鈥?/div>
VREF
CAZ
BUF
CAZ
INTEGRATOR
鈥?/div>
CMPTR 1
+
+
鈥?/div>
+
CINT
CINT
CONTROL LOGIC
CONVERTER STATE
B
0
ZERO INTEGRATOR OUTPUT
1
AUTO-ZERO
0
SIGNAL INTEGRATE
1
DEINTEGRATE
2
3
4
5
6
7
DGND
ORDERING INFORMATION
Part No.
TC500ACOE
TC500ACPE
TC500COE
TC500CPE
TC510COG
TC510CPF
TC514COI
TC514CPJ
TC500EV
Package
16-Pin SOIC
16-Pin Plastic DIP (Narrow)
16-Pin SOIC
16-Pin Plastic DIP (Narrow)
24-Pin SOIC
24-Pin Plastic DIP (300 Mil.)
Temp. Range
0擄C to +70擄C
0擄C to +70擄C
0擄C to +70擄C
0擄C to +70擄C
0擄C to +70擄C
0擄C to +70擄C
28-Pin SOIC
0擄C to +70擄C
28-Pin Plastic DIP (300 Mil.)
0擄C to +70擄C
Evaluation Kit for TC500/500A/510/514
FUNCTIONAL BLOCK DIAGRAM
CREF
A0
A1
A
0
0
1
1
+
CREF
+
VREF
鈥?/div>
CREF
BUFFER
鈥?/div>
CH1 +
+
CH2
+
CH3
+
CH4
鈥?/div>
CH1
CH2 鈥?/div>
CH3 鈥?/div>
CH4 鈥?/div>
ACOM
SWR SWR
DIF.
MUX
(TC514)
SWI
鈥?/div>
SWRI
+
SWRI
+
TC500
TC500A
TC510
CMPTR 2
TC514
鈥?/div>
LEVEL
SHIFT
CMPTR
OUTPUT
SWZ
+
SWRI
鈥?/div>
SWRI
SW1
SWIZ SWZ
POLARITY
DETECTION
ANALOG
SWITCH
CONTROL
SIGNALS
SWI
VS
OSC
DC-TO-DC
CONVERTER
(TC510 & TC514)
PHASE
DECODING
LOGIC
鈥?/div>
VOUT
CAP鈥?CAP+
VSS
1.0碌F
(TC500
TC500A)
1.0碌F
A
B
鈥?/div>
COUT
CONTROL LOGIC
TC500/A/510/514-3
10/3/96
8
3-19
TELCOM SEMICONDUCTOR, INC.
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