鈥?/div>
Signal-Noise Ratio鈥?.鈥︹€?.....74dBc @126MHz
Signal Input鈥︹€︹€︹€︹€?000MSPS, 14bits LVDS
Spur Free Dynamic Range鈥?..75dBc @126MHz
Clock Input Drive.. 0 to +13dBm, 25鈩?differential
Full Scale Output鈥︹€?.鈥?2dBm, 50鈩?differential
Voltage Reference鈥︹€?..2.5V Bandgap On-Chip
Power Dissipation 鈥?.鈥︹€︹€︹€︹€︹€︹€︹€︹€?1.8W
Technology 鈥︹€︹€︹€︹€︹€?0.5 碌m SiGe BiCMOS
Packaging......96 ball, Pb-free, Cavity-down BGA
Description
As shown in the functional block diagram below, the
TC2411 features a 5-Bit Unary + 9-Bit Binary R2R
architecture. 14-bit straight binary data can be input
to the DAC at a sample rate of up to 1 GSPS. The
DAC provides low-noise and low-spurious
performance with digital IF input signals across the
first Nyquist band.
The highly linear analog output produced by the
TC2411 may be filtered externally to reject the signal
image, and is suitable for single-stage upconversion
applications.
Ordering Information
PART
NUMBER
TC2411-IB
TC2411-KIT
TEMP RANGE
(擄C)
-40擄C to +85擄C
+25C
PACKAGE
96 ball Pb-free
BGA
CLOCK
SPEED
1000 MHz
Evaluation Kit
5
Digital
Input
Clock In
2.5V
Ref Out
2.5V
Ref In
14
Buffer
+
Register
5 MSB
Decode
31
Register
31
Unary
9
Analog
Output
R-2R
Ladder
Buf
9
Binary
Amp
Band
Gap
Amp
Ref
Cell
Figure 1: TC2411 Functional Block Diagram
1
Copyright 2004 TelASIC Communications, Inc. All rights reserved. www.telasic.com
Tel: 310.955.3838
.
Specifications subject to change without notice.