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TB5R1LDW Datasheet

  • TB5R1LDW

  • QUAD DIFFERENTIAL PECL RECEIVERS

  • 11頁

  • TI

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TB5R1, TB5R2
www.ti.com
SLLS588B 鈥?NOVEMBER 2003 鈥?REVISED MAY 2004
QUAD DIFFERENTIAL PECL RECEIVERS
FEATURES
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Functional Replacements for the Agere
BRF1A, BRF2A, BRS2A, and BRS2B
Pin Equivalent to General Trade 26LS32
High Input Impedance Approximately 8 k鈩?/div>
4-ns Maximum Propagation Delay
TB5R1 Provides 50-mV Hysteresis
TB5R2 With -125-mV Threshold Offset for
Preferred State Output
-1.1-V to 7.1-V Common Mode Range
Single 5-V
鹵10%
Supply
Slew Rate Limited (1 ns min 80% to 20%)
TB5R2 Output Defaults to Logic 1 When In-
puts Left Open or Shorted to V
CC
or GND
ESD Protection HBM > 3 kV, CDM > 2 kV
Operating Temperature Range: -40擄C to 85擄C
Available in Gull-Wing SOIC (JEDEC MS-013,
DW) and SOIC (D) Package
DESCRIPTION
These quad differential receivers accept digital data
over balanced transmission lines. They translate
differential input logic levels to TTL output logic
levels.
The TB5R1 is a pin- and function-compatible replace-
ment for the Agere systems BRF1A and BRF2A; it
includes 3-kV HBM and 2-kV CDM ESD protection.
The TB5R2 is a pin- and function-compatible replace-
ment for the Agere systems BRS2A and BRS2B and
incorporates a 125-mV receiver input offset, preferred
state output, 3-kV HBM and 2-kV CDM ESD protec-
tion. The TB5R2 preferred state feature places the
high state when the inputs are open, shorted to
ground, or shorted to the power supply.
The power-down loading characteristics of the re-
ceiver input circuit are approximately 8 k鈩?relative to
the power supplies; hence they do not load the
transmission line when the circuit is powered down.
The packaging for these differential line receivers
include a 16-pin gull wing SOIC (DW) and SOIC (D).
The enable inputs of this device include internal
pullup resistors of approximately 40 k鈩?that are
connected to V
CC
to ensure a logical high level input
if the inputs are open circuited.
FUNCTIONAL BLOCK DIAGRAM
AI
AI
BI
AO
BO
CO
DO
APPLICATIONS
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Digital Data or Clock Transmission Over Bal-
anced Lines
PIN ASSIGNMENTS
D PACKAGE
(TOP VIEW)
AI
AI
AO
E1
BO
BI
BI
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
DI
DI
DO
E2
CO
CI
CI
BI
C1
C1
D1
D1
E1
E2
ENABLE TRUTH TABLE
E1
0
1
0
1
E2
0
0
1
1
CONDITION
Active
Active
Disabled
Active
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 漏 2003鈥?004, Texas Instruments Incorporated

TB5R1LDW 產(chǎn)品屬性

  • 40

  • 集成電路 (IC)

  • 接口 - 驅(qū)動(dòng)器,接收器,收發(fā)器

  • -

  • 接收器

  • 0/4

  • -

  • 4.5 V ~ 5.5 V

  • 表面貼裝

  • 16-SOIC(0.295",7.50mm 寬)

  • 16-SOIC

  • 管件

  • 296-17535-5

TB5R1LDW相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
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