T89C51RB2/RC2
8-bit Microcontroller with 16 Kbytes/ 32 Kbytes FLASH
1. Description
T89C51RB2/RC2 is a high performance FLASH version
of the 80C51 8-bit microcontrollers. It contains a 16K
or 32Kbytes Flash memory block for program and data.
The 16 Kbytes or 32 Kbytes FLASH memory can be
programmed either in parallel mode or in serial mode
with the ISP capability or with software. The
programming voltage is internally generated from the
standard V
CC
pin.
The T89C51RB2/RC2 retains all features of the 80C52
with 256 bytes of internal RAM, a 7-source 4-level
interrupt controller and three timer/counters.
In addition, the T89C51RB2/RC2 has a Programmable
Counter Array, an XRAM of 1024 byte, a Hardware
Watchdog Timer, a Keyboard Interface, a SPI Interface,
a more versatile serial channel that facilitates
multiprocessor communication (EUART) and a speed
improvement mechanism (X2 mode).
Pinout is the standard 40/44 pins of the C52.
The fully static design of the T89C51RB2/RC2 allows
to reduce system power consumption by bringing the
clock frequency down to any value, even DC, without
loss of data.
The T89C51RB2/RC2 has 2 software-selectable modes
of reduced activity and 8 bit clock prescaler for further
reduction in power consumption. In the Idle mode the
CPU is frozen while the peripherals and the interrupt
system are still operating. In the power-down mode the
RAM is saved and all other functions are inoperative.
The added features of the T89C51RB2/RC2 make it more
powerful for applications that need
pulse width
modulation, high speed I/O and counting capabilities
such as alarms, motor control, corded phones, smart card
readers.
2. Features
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80C52 Compatible
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8051 pin and instruction compatible
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Four 8-bit I/O ports
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Three 16-bit timer/counters
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256 bytes scratch pad RAM
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10 Interrupt sources with 4 priority levels
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Dual Data Pointer
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On-chip 1024 bytes expanded RAM (XRAM)
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Software selectable size (0, 256, 512, 768, 1024
bytes)
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256 bytes selected at reset for TS87C51RB2/RC2
compatibility
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Variable length MOVX for slow RAM/peripherals
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ISP (In System Programming) using standard V
CC
power supply.
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Keyboard interrupt interface on port P1
SPI Interface (Master / Slave Mode)
8-bit clock prescaler
Improved X2 mode with independant selection for
CPU and each peripheral
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High Speed Output,
Compare / Capture,
Pulse Width Modulator,
Watchdog Timer Capabilities
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Boot ROM contains low level FLASH programming
routines and a default serial loader
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40 MHz in standard mode
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20 MHz in X2 mode (6 clocks/machine cycle)
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Programmable Counter Array 5 Channels with:
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High-Speed Architecture
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16K/32K bytes on-chip FLASH program / data
Memory
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Byte and page (128 bytes) erase and write
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100k write cycles
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Asynchronous port reset
Full duplex Enhanced UART
Dedicated Baud Rate Generator for UART
Low EMI (inhibit ALE)
Rev. B - 30-Mar-01
1
Preliminary
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