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T431616D-6C Datasheet

  • T431616D-6C

  • 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM

  • 74頁(yè)

  • TMT

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tm
TE
CH
T431616D/E
SDRAM
FEATURES
Fast access time: 5/6/7 ns
鈥?/div>
Fast clock rate: 200/166/143 MHz
鈥?/div>
Self refresh mode: standard and low power
鈥?/div>
Internal pipelined architecture
鈥?/div>
512K word x 16-bit x 2-bank
鈥?/div>
Programmable Mode registers
- CAS# Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
鈥?/div>
Individual byte controlled by LDQM and UDQM
鈥?/div>
Auto Refresh and Self Refresh
鈥?/div>
4096 refresh cycles/64ms
鈥?/div>
CKE power down mode
鈥?/div>
JEDEC standard +3.3V
鹵
0.3V power supply
鈥?/div>
Interface: LVTTL
鈥?/div>
50-pin 400 mil plastic TSOP II package
鈥?/div>
60-ball, 6.4x10.1mm VFBGA package
鈥?/div>
Lead Free Package available for both TSOP II and
VFBGA
鈥?/div>
Low Operating Current for T431616E
1M x 16 SDRAM
512K x 16bit x 2Banks Synchronous DRAM
GRNERAL DESCRIPTION
The T431616D/E SDRAM is a high-speed CMOS
synchronous DRAM containing 16 Mbits. It is internally
configured as a dual 512K word x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the
512K x 16 bit banks is organized as 2048 rows by 256
columns by 16 bits. Read and write accesses to the
SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Accesses begin
with the registration of a BankActivate command which
is then followed by a Read or Write command.
The T431616D/E provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy to
use. By having a programmable mode register, the
system can choose the most suitable modes to maximize
its performance. These devices are well suited for
applications requiring high memory bandwidth and
particularly well suited to high performance PC
applications
Key Specifications
T431616D/E
t
CK3
t
RAS
t
AC3
t
RC
Clock Cycle time(min.)
Row Active time(max.)
Access time from CLK(max.)
Row Cycle time(min.)
-5/6/7
5/6/7ns
35/42/42 ns
4.5/5/5.5 ns
48/54/63 ns
ORDERING INFORMATION
Part Number
T431616D-5S/C
T431616D-5SG/CG
T431616D-6S/C
T431616D-6SG/CG
T431616D-7S/C
T431616D-7SG/CG
T431616E-7S/C
T431616E-7SG/CG
G : indicates Lead Free Package
Frequency
200MHz
200MHz
166MHz
166MHz
143MHz
143MHz
143MHz
143MHz
Package
TSOP II / VFBGA
TSOP II / VFBGA
TSOP II / VFBGA
TSOP II / VFBGA
TSOP II / VFBGA
TSOP II / VFBGA
TSOP II / VFBGA
TSOP II / VFBGA
TM Technology Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A

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