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T35L6432A-5T Datasheet

  • T35L6432A-5T

  • 64K x 32 SRAM

  • 15頁

  • TMT

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tm
TE
CH
T35L6432A
SYNCHRONOUS
BURST SRAM
FEATURES
隆E
ast Access times: 4.5, 5, 6, 7, and 8ns
F
隆E
ast clock speed: 125,100, 83, 66, and 50 MHz
F
隆E
rovide high performance 3-1-1-1 access rate
P
隆E
ast
OE
access times: 4.5, 5 and 6ns
F
隆E
ingle 3.3V +10%/-5% power supply
S
隆E
ommon data inputs and data outputs
C
隆E
YTE WRITE ENABLE and GLOBAL WRITE
B
control
隆E
hree chip enables for depth expansion and
T
address pipelining
隆E
ddress, control, input, and output pipelined
A
registers
隆E
nternally self-timed WRITE CYCLE
I
隆E
RITE pass-through capability
W
隆E
urst control pins ( interleaved or linear burst
B
sequence)
隆E
igh density, high speed packages
H
隆E
ow capacitive bus loading
L
隆E
igh 30pF output drive capability at rated access
H
time
隆E
NOOZE MODE for reduced power standby
S
隆E
Single cycle disable ( Pentium
TM
BSRAM
compatible )
64K x 32 SRAM
3.3V supply, fully registered inputs and
outputs, burst counter
PIN ASSIGNMENT
(Top View)
ADSC
ADSP
BW4
BW3
BW2
BW1
GW
BWE
CE2
VCC
VSS
ADV
A8
CLK
CE
CE2
OE
A6
A7
A9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
DQ17
DQ18
VCCQ
VSSQ
DQ19
DQ20
DQ21
DQ22
VSSQ
VCCQ
DQ23
DQ24
NC
VCC
NC
VSS
DQ25
DQ26
VCCQ
VSSQ
DQ27
DQ28
DQ29
DQ30
VSSQ
VCCQ
DQ31
DQ32
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
NC
DQ16
DQ15
VCCQ
VSSQ
DQ14
DQ13
DQ12
DQ11
VSSQ
VCCQ
DQ10
DQ9
VSS
NC
VCC
ZZ
DQ8
DQ7
VCCQ
VSSQ
DQ6
DQ5
DQ4
DQ3
VSSQ
VCCQ
DQ2
DQ1
NC
100-pin QFP
or
100-pin TQFP
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE
VSS
VCC
A10
A11
A12
A13
A14
A15
A0
NC
NC
NC
NC
NC
A5
A4
A3
A2
A1
OPTIONS
TIMING
4.5ns access/8ns cycle
5ns access/10ns cycle
6ns access/12ns cycle
7ns access/15ns cycle
8ns access/20ns cycle
Package
100-pin QFP
100-pin TQFP
MARKING
-4.5
-5
-6
-7
-8
Q
T
GENERAL DESCRIPTION
The Taiwan Memory Technology Synchronous
Burst RAM family employs: high-speed, low power
CMOS design using advanced triple-layer
polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two
high valued resistors.
The T35L6432A SRAM integrates 65536 x 32
SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst
operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered
clock input (CLK). The synchronous inputs include
all addresses, all data inputs, address-pipelining
P. 1
Publication Date: DEC. 1998
Revision: A
Part Number Examples
PART NO.
Pkg. BURST SEQUENCE
T35L6432A-5Q Q Interleaved
(MODE=NC or VCC)
T35L6432A-5T T
Linear (MODE=GND)
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.

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