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T2316162A-50 Datasheet

  • T2316162A-50

  • 1024K x 16 DYNAMIC RAM EDO PAGE MODE

  • 139.88KB

  • 13頁(yè)

  • TMT

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tm
TE
CH
T2316162A
DRAM
FEATURES
鈥?/div>
Industry-standard x 16 pinouts and timing
functions.
鈥?/div>
Single 5V (鹵10%) power supply.
鈥?/div>
All device pins are TTL- compatible.
鈥?/div>
1K-cycle refresh in 16ms.
鈥?/div>
Refresh modes: RAS only, CAS BEFORE
RAS (CBR) and HIDDEN.
鈥?/div>
Extended data-out (EDO) PAGE MODE access
cycle.
鈥?/div>
BYTE WRITE and BYTE READ access cycles.
1024K x 16 DYNAMIC RAM
EDO PAGE MODE
GENERAL DESCRIPTION
The T2316162A is a randomly accessed solid state
memory containing 16,777,216 bits organized in a
x16 configuration. The T2316162A has both
BYTE WRITE and WORD WRITE access cycles
via two CAS pins. It offers Fast Page mode with
Extended Data Output.
The T2316162A CAS function and timing are
determined by the first CAS to transition low and
by the last to transition back high. Use only one of
the two CAS and leave the other staying high
during WRITE will result in a BYTE WRITE.
CASL transiting low in a WRITE cycle will write
data into the lower byte (DQ0~DQ7), and CASH
transiting low will write data into the upper byte
(DQ8~DQ15).
OPTION
TIMING
MARKING
45ns
-45
50ns
-50
60ns
-60
PACKAGE
42-pin SOJ
J
44/50-pin TSOPII
S
PIN ASSIGNMENT ( Top View )
V
DD
1
2
3
4
5
6
7
8
9
10
11
50
49
48
47
46
45
44
43
42
41
40
Vss
DQ15
DQ14
DQ13
DQ12
Vss
DQ11
DQ10
DQ9
DQ8
NC
V
DD
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Vss
DQ15
DQ14
DQ13
DQ12
Vss
DQ11
DQ10
DQ9
DQ8
NC
CASL
CASH
OE
A9
A8
A7
A6
A5
A4
Vss
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
V
DD
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
CASL
CASH
OE
A9
A8
A7
A6
A5
A4
Vss
TM Technology Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: APR. 2002
Revision:E

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