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T15M1024A-70H Datasheet

  • T15M1024A-70H

  • 128K X 8 LOW POWER CMOS STATIC RAM

  • 13頁(yè)

  • TMT

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tm
TE
CH
T15M1024A
SRAM
FEATURES
鈥?/div>
Low-power consumption
- Active: 40mA at 55ns
- Stand-by: (CMOS input/output)
0 ~ +70
擄C
= 15uA
-40 ~ +85
擄C
= 20uA
鈥?/div>
55/70/100 ns access time
鈥?/div>
Equal access and cycle time
鈥?/div>
Single +5V (鹵10%) Power Supply
鈥?/div>
TTL compatible , Tri-state output
鈥?/div>
Common I/O capability
鈥?/div>
Automatic power-down when deselected
鈥?/div>
Available in 32-pin SOP ,TSOP-I(8x20mm),
TSOP-I(8x13.4mm) and DIP (600 mil) package.
128K X 8 LOW POWER
CMOS STATIC RAM
GENERAL DESCRIPTION
The T15M1024A is a very Low Power CMOS
Static RAM organized as 131,072 words by 8 bits.
That operates on a wide voltage range from +5V
(鹵10%) power supply, Fabricated using high
performance
CMOS
technology,
Inputs
and
three-state outputs are TTL compatible and allow
for direct interfacing with common system bus
structures. Data retention is guaranteed at a power
supply voltage as low as 1.5V.
BLOCK DIAGRAM
PART NUMBER EXAMPLES
PART NO.
T15M1024A-55D
T15M1024A-70H
T15M1024A-100P
T15M1024A-100N
T15M1024A-55DI
T15M1024A-70HI
T15M1024A-100PI
T15M1024A-100NI
PACKAGE
CODE
D=SOP
H=TSOP-I(8x20)
P=TSOP-I(8x13.4)
N=DIP (600 mil)
D=SOP
H=TSOP-I(8x20)
P=TSOP-I(8x13.4)
N=DIP (600 mil)
Operating
Temperature
0 ~ +70
擄C
Vcc
Vss
A0
.
.
.
A16
WE
OE
CE1
CE2
DECODER
CORE
ARRAY
-40 ~ +85
擄C
CONTROL
CIRCUIT
DATA I/O
I/O1
..
I/O8
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 1
Publication Date: FEB. 2002
Revision:A

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