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SY89538L Datasheet

  • SY89538L

  • 3.3V PRECISION LVPECL AND LVDS PROGRAMMABLE MULTIPLE OUTPUT ...

  • 23頁

  • MICREL   MICREL

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SY89538L
3.3V Precision LVPECL and LVDS
Programmable Multiple Output Bank Clock
Synthesizer and Fanout Buffer with Zero Delay
General Description
The SY89538L integrated programmable clock
synthesizer and fanout is part of a precision PLL-
based clock generation family optimized for
enterprise switch, router, and multiprocessor server
applications. This family is ideal for generating
internal system timing requirements up to 750MHz for
multiple ASICs, FPGAs, and NPUs. These devices
integrate the following blocks into a single monolithic
IC:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
PLL (Phase-Lock-Loop) based synthesizer
Zero-delay MUX and feedback capability
1:4 LVPECL fanout
1:3 LVDS fanout
Clock generator (dividers)
Logic translation (LVPECL, LVDS)
Precision Edge
廬
Features
鈥?/div>
Integrated programmable synthesizer with multiple
output dividers, fanout buffers, and clock drivers
鈥?/div>
Zero-delay capability: 29.375MHz to 756MHz
鈥?/div>
Reference clock input: 9.325MHz to 756MHz
鈥?/div>
Input MUX accepts a reference and a crystal
(XTAL) source
鈥?Ideal for reference backup clock source or
system test frequency source
鈥?Patent-pending unique input MUX isolates XTAL
and reference inputs which minimizes crosstalk
鈥?/div>
Guaranteed AC performance:
鈥?Output frequency range: 29.375MHz to 756MHz
鈥?<150ps
PP
total jitter
鈥?<6ps
RMS
cycle-to-cycle jitter (XTAL Input)
鈥?<8ps
PP
deterministic jitter
鈥?<0.7ps
RMS
crosstalk induced jitter
鈥?<75ps output-to-output skew
鈥?/div>
TTL/CMOS-compatible control logic
鈥?/div>
Five-independently programmable output
frequency banks:
鈥?Four differential LVPECL output banks
鈥?One differential LVDS output bank with three
output pairs
鈥?/div>
Output bank synchronization control pin
鈥?/div>
Output enable
鈥?/div>
3.3V 鹵10% power supply (2.5V output capable)
鈥?/div>
Guaranteed over the industrial temperature range
(-40擄C to +85擄C)
鈥?/div>
Available in a 64-pin EPAD-TQFP
Five-independently programmable output
banks
This level of integration minimizes additive jitter and
part-to-part
skew
associated
with
discrete
alternatives, resulting in superior system-level timing
with reduced board space and power. For
applications that do not require a zero-delay function,
see the SY89537L.
All support documentation can be found on
Micrel鈥檚 web site at:
www.micrel.com.
Applications
鈥?/div>
Enterprise routers, switches, servers and
workstations
鈥?/div>
Parallel processor-based systems
鈥?/div>
Internal system clock generation for ASICs, NPUs
and FPGAs
Markets
鈥?/div>
LAN/WAN
鈥?/div>
Enterprise servers
鈥?/div>
Test and measurement
Precision Edge is a registered trademark of Micrel, Inc.
MLF and
MicroLeadFrame
are trademarks of Amkor Technology, Inc.
Micrel Inc. 鈥?2180 Fortune Drive 鈥?San Jose, CA 95131 鈥?USA 鈥?tel +1 (408) 944-0800 鈥?fax + 1 (408) 474-1000 鈥?http://www.micrel.com
October 2005
M9999-101105-B
hbwhelp@micrel.com
or (408) 955-1690

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