ClockWorks鈩?/div>
SY89425
DESCRIPTION
Micrel-Synergy's SY89425 Dual Phase Locked Loop
(PLL) consists of two totally separate, SONET compliant
622.08MHz clock generators on one chip. The user may
select to power both PLLs or PLL A only. Each PLL
produces a low-jitter OC-12/STS-12 clock rate from an
input reference clock of 38.88, 51.84, or 77.76MHz. When
using both PLLs, it is not necessary that they share a
common reference clock (e.g., PLL A may operate from an
STS-1 reference of 51.84MHz, while PLL B operates from
an OC-3/STS-3 reference of 77.76MHz).
The SY89425 operates from a single +5 volt supply, and
requires only a simple series RC loop filter for each PLL.
Coupling Micrel-Synergy's advanced PLL technology
with our proprietary ASSET鈩?bipolar process has produced
a clock generator IC which exceeds applicable Bellcore
and ANSI specifications, while setting a new standard for
performance and flexibility.
TYPICAL APPLICATION
+5V
+5V
PIN CONFIGURATION
FLTRAN
FLTRAP
RSTA
V
CCA
GND
GND
RFCKA
(TTL)
VCCA
VCCOA
RSTA
(TTL)
25 24 23 22 21 20 19
V
CCA
GND
CLOCK IN
0.1uF
SEL39A
SEL78A
RFCKA
V
CCA
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
16
CK622AP
CK622AN
V
CCOA
GND
V
CCOB
CK622BN
CK622BP
FLTRAN
FLTRAP
PLL A
CK622AP
(PECL)
CK622AN
PLCC
TOP VIEW
15
14
13
12
RFCKB
622.08MHz
SEL78B
SEL39B
500鈩?/div>
SEL39A
(TTL)
SEL78A
(TTL)
2X 50鈩?/div>
GND
GND
FLTRBN
FLTRBP
RSTB
V
CCB
+3V
PLL B
GND
AGND
(SAME AS PLL A)
V
CCB
Rev.: E
Amendment: /0
1
Issue Date: August, 1998
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