ClockWorks鈩?/div>
SY89423V
DESCRIPTION
The SY89423V device consists of two identical, low
jitter, digital Phase Locked Loops based on Micrel-Synergy's
differential PLL technology. Each PLL is capable of
operating in the 30MHz to 560MHz reference input
frequency range, and is independent of the other, and is
configurable separately. The PLLs can be configured to be
matched in all regards, or can be configured so that PLLB
is used as a frequency doubler, while PLLA is used to
regenerate the undoubled frequency. Each PLL is capable
of operating up to 2000MHz with the HFIN input and an
external VCO.
Two reference inputs (RINX and RINX), two feedback
inputs (FINX and FINX), two high frequency inputs (HFINX
and HFINX), two filter pins (F1X and F2X), two normal
outputs (FOUTX and FOUTX), and two high frequency
outputs (HFOUTX and HFOUTX) are provided for each of
the two PLLs. The reference, feedback, and high frequency
inputs can be used as either differential or single-ended
inputs. External reference voltage generators are required
for single-ended drive.
Feedback for the loops is realized by connecting FOUTX,
FOUTX to FINX, FINX by means of external circuitry. This
allows the user the flexibility of inserting additional circuitry
off-chip in the feedback paths, such as an additional
divider. Pulldown resistors are required for the FOUTX and
FOUTX pins, and for the HFOUTX and HFOUTX pins.
Use of a phase-frequency detector in each PLL results
in excellent locking and tracking characteristics. Error
correction voltages are generated by the detector if either
phase or frequency deviations occur. The VCO in each PLL
has a frequency range covering more than a 2:1 ratio from
480MHz to 1120MHz.
Select pins S1A, S2A, S1B, S2B, and S3B are used to
program the N dividers for optimum VCO operation, in
other words with the VCO operating in the center of its
range. When both S3B and S5B are low, PLLB is identical
to PLLA. When S5B is high, the 2X frequency multiplication
option is enabled. Select pins S3A and S4B enable the HF
inputs for PLLA and PLLB respectively, which allows the
use of an external VCO in either PLL. All the select pins are
TTL inputs.
APPLICATIONS
s
Workstations
s
Advanced communications
s
High-performance computing
PIN CONFIGURATION
FOUTA
FOUTA
FOUTB
FOUTB
V
CCOA
V
CCOB
V
CC
V
CC
NC
NC
6
NC
HFOUTA
HFOUTA
S1A
S2A
F1A
F2A
S3A
S5B
HFINA
HFINA
7
8
9
10
11
12
13
14
15
16
17
5
4
3
2
1
44 43 42 41 40
39
38
37
36
NC
HFOUTB
HFOUTB
S1B
S2B
F1B
F2B
S3B
S4B
HFINB
HFINB
NC
35
34
33
32
31
30
29
FINB
TOP VIEW
PLCC
J44-1
18 19 20 21 22 23 24 25 26 27 28
RINA
RINA
RINB
RINB
V
EE
V
EE
FINA
FINA
NC
FINB
Rev.: G
Amendment: /0
1
Issue Date: May 2000
MICREL
1
2
3
4
5
6
7
8
