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SY89421VZCTR Datasheet

  • SY89421VZCTR

  • 5V/3.3V HIGH-PERFORMANCE PHASE LOCKED LOOP

  • 8頁

  • MICREL   MICREL

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5V/3.3V
HIGH-PERFORMANCE
PHASE LOCKED LOOP
FEATURES
s
3.3V and 5V power supply options
s
1.12GHz maximum VCO frequency
s
30MHz to 560MHz reference input operating
frequency
s
External 2.0GHz VCO capability
s
Low jitter differential design
s
Frequency doubler mode
s
PECL Differential output
s
External loop filter optimizes performance/cost
s
Available in 20-pin SOIC package
ClockWorks鈩?/div>
SY89421V
DESCRIPTION
The SY89421V is a digital Phase Locked Loop based on
Micrel-Synergy's differential PLL technology. It is capable
of operating in the 30MHz to 560MHz reference input
frequency range, and up to 2000MHz with the HFIN input
and an external VCO. Use of a phase-frequency detector
results in excellent PLL locking and tracking characteristics.
Error correction voltages are generated by the detector if
either phase or frequency deviations occur. The VCO has
a frequency range covering more than a 2:1 ratio from
480MHz to 1120MHz.
Feedback for the loop is realized by connecting FOUT,
FOUT to FIN, FIN by means of external circuitry. This
allows the flexibility of inserting additional circuitry off-chip
in the feedback paths, such as an additional divider and/or
buffer. Pulldown resistors are required for the FOUT and
FOUT pins. High frequency inputs HFIN, HFIN and
corresponding outputs HFOUT, HFOUT are featured for
use with external components such as an active loop filter
and a high frequency VCO.
Select pins S1 and S2 are used to program the N divider
for optimum VCO operation, in other words with the VCO in
the center of its range. Select pin S3 allows bypassing the
N divider enabling the PLL to output the VCO directly.
Select pin S4 is used to select off-chip or on-chip VCO.
Select pin S5 enables the divide-by-two prescaler, which is
useful in frequency doubling applications. All Select pins
are TTL compatible.
APPLICATIONS
s
Workstations
s
Advanced communications
s
High-performance computing
PIN CONFIGURATION
S1
FIN
FIN
V
EE
F1
F2
S5
HFIN
HFIN
1
2
3
4
5
6
7
8
9
20
19
18
17
S2
RIN
RIN
S3
V
CC
FOUT
FOUT
V
CCO
HFOUT
HFOUT
TOP VIEW
SOIC
Z20-1
16
15
14
13
12
11
S4 10
Rev.: F
Amendment: /0
1
Issue Date: May 2000

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