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SY69952ZC Datasheet

  • SY69952ZC

  • OC-3/STS-3 CLOCK RECOVERING TRANSCEIVER

  • 7頁

  • MICREL   MICREL

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OC-3/STS-3
CLOCK RECOVERING
TRANSCEIVER
FEATURES
s
A complete ATM compatible single chip Transmitter
and Receiver
s
Seamless operation with PMC-Sierra PM5345, VLSI
VNS67200, IgT WAC-013-B/WAC-413-A and NEC
碌
PD98402 UNI Processors
s
Supports clock and data recovery from 51.84 Mbit/s
or 155.52 Mbit/s NRZ or NRZI data stream
s
155.52MHz clock multiplication from 19.44MHz
source or 51.84MHz clock multiplication from
6.48MHz source
s
Line Receiver Inputs: No external buffering needed
s
Differential output buffering
s
Link Status Indication
s
Loop-back testing
s
100K ECL compatible I/O
s
Single +5 volt power supply
s
Replacement for Cypress CY7B952
s
The SY69952 complies with Bellcore, ITU/CCITT &
ANSI specifications
s
Available in 28-pin SOIC package
SY69952
DESCRIPTION
Micrel-Synergy's SY69952 contains fully integrated
transmitter and receiver functions designed to provide
clock recovery and generation for either 51.84Mbit/s OC/
STS-1 or 155.52Mbit/s OC/STS-3 SONET/SDH
(SY69952) and ATM applications.
On-chip clock generation is performed by a low-jitter
phase-locked loop (PLL) allowing use of 19.44MHz
reference for 155.52MHz generation or a 6.48MHz
reference for 51.84MHz generation. Clock recovery is
performed by synchronizing the on-chip VCO directly to
the incoming data stream.
The SY69952 meets the jitter compliance criteria of
Bellcore, ITU/CCITT and ANSI standards. Low jitter is
ensured by Micrel-Synergy's advanced PLL technology
and positive ECL (PECL) I/O.
Micrel-Synergy's circuit design techniques coupled with
ASSET鈩?bipolar technology result in ultra-fast
performance with low noise and low power dissipation.
FUNCTIONAL BLOCK DIAGRAM
PLL2+
PLL2-
PIN CONFIGURATION
LOOP
MODE
ROUT+
ROUT-
ROUT+
ROUT-
RIN+
RIN-
RCLK+
RCLK-
PLL
RSER+
RSER-
RIN+
RIN-
MODE
V
CC
CD
LOOP
REFCLK-
REFCLK+
TOUT-
TOUT+
PLL1+
PLL1-
CD
LFI
RECEIVE
TRANSMIT
TOUT+
TOUT-
PLL
x8
TSER+
TSER-
TCLK+
TCLK-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
TOP VIEW
SOIC
22
21
20
19
18
17
16
15
RCLK-
RCLK+
RSER-
RSER+
LFI
V
CC
V
EE
V
CC
TCLK-
TCLK+
TSER+
TSER-
PLL2+
PLL2-
REFCLK+
REFCLK-
PLL1+
PLL1-
Rev.: M
Amendment: /0
1
Issue Date: October, 1998

SY69952ZC 產(chǎn)品屬性

  • 27

  • 集成電路 (IC)

  • 時(shí)鐘/計(jì)時(shí) - 專用

  • -

  • 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器

  • 是

  • 以太網(wǎng)，SONET/SDH，ATM 應(yīng)用

  • PECL

  • PECL

  • 1

  • 1:3

  • 是/是

  • 155.52Mbps

  • 4.75 V ~ 5.25 V

  • 0°C ~ 85°C

  • 表面貼裝

  • 28-SOIC（0.295"，7.50mm 寬）

  • 28-SOIC

  • 管件

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