ClockWorks鈩?/div>
PRELIMINARY
SY10H842L
SY100H842L
DESCRIPTION
The SY10/100H842L are single supply, low skew
translating 1:4 clock drivers.
The devices feature a 24mA TTL output stage, with
AC performance specified into a 20pF load capacitance.
A HIGH on the enable pin (EN) forces all outputs LOW.
As frequencies increase to 40MHz and above, precise
timing and shaping of clock signals becomes extremely
important. The H842 solves several clock distribution
problems such as minimizing skew 300ps), maximizing
clock fanout (24mA drive), and precise duty cycle control
through a proprietary differential internal design.
The 10K version is compatible with 10KH ECL logic
levels. The 100K version is compatible with 100K levels.
BLOCK DIAGRAM
TTL Outputs
PIN CONFIGURATION
G
T
EN
1
2
3
4
5
6
7
8
SOIC
Z16-1
16
15
14
13
12
11
10
9
Q
3
G
T
Q
2
V
T
V
T
Q
1
G
T
Q
0
Q
0
G
E
V
E
D
Q
1
D
V
BB
G
T
Q
2
PIN NAMES
Q
3
ECL Input
D
D
V
BB
EN
Pin
G
T
V
T
V
E
G
E
D, D
V
BB
Q
0
- Q
3
EN
Function
TTL Ground (0V)
TTL V
CC
(+3.3V)
ECL V
CC
(+3.3V)
ECL Ground (0V)
Signal Input (PECL)
V
BB
Reference Output (PECL)
Signal Outputs (TTL)
Enable Input (PECL)
Rev.: C
Amendment: /1
1
Issue Date: August, 1999