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PRELIMINARY
SY10H641L
SY100H641L
FEATURES
s
3.3V power supply
s
PECL-to-TTL version of popular ECLinPS E111
s
Guaranteed low skew specification
s
Latched input
s
Differential ECL internal design
s
V
BB
output for single-ended operation
s
Reset/enable
s
Extra TTL and ECL power/ground pins
s
Choice of ECL compatibility: MECL 10KH (10Hxxx)
or 100K (100Hxxx)
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100H641L are single supply, low skew
translating 1:9 clock drivers. Devices in the Micrel-
Synergy H600 translator series utilize the 28-lead PLCC
for optimal power pinning, signal flow-through and
electrical performance.
The devices feature a 24mA TTL output stage with
AC performance specified into a 20pF load capacitance.
A latch is provided on-chip. When LEN is LOW (or left
open, in which case it is pulled LOW by the internal pull-
downs), the latch is transparent. A HIGH on the enable
pin (/EN) forces all outputs LOW.
The 10H version is compatible with MECL 10KH ECL
logic levels. The 100H version is compatible with 100K
levels.
BLOCK DIAGRAM
TTL Outputs
Q
0
PIN CONFIGURATION
Q
6
V
T
Q
7
V
T
Q
8
G
T
18
17
16
25 24 23 22 21 20 19
G
T
Q
1
26
27
28
1
2
3
4
5
6
7
8
9
10 11
G
T
Q
5
V
T
Q
4
V
T
TOP VIEW
PLCC
15
14
13
12
V
BB
D
D
V
E
LEN
G
E
EN
Q
2
Q
3
G
T
G
T
Q
2
V
T
Q
1
V
T
PECL Input
D
D
V
BB
Q
5
LEN
EN
Q
6
D
Q
Q
4
PIN NAMES
Pin
G
T
V
T
V
E
G
E
D, /D
Function
TTL Ground (0V)
TTL V
CC
(+3.0V)
ECL V
CC
(+3.0V)
ECL Ground (0V)
Signal Input (PECL)
V
BB
Reference Output (PECL)
Signal Outputs (TTL)
Enable Input (PECL)
Latch Enable Input (PECL)
Q
7
V
BB
Q
0
鈥?Q
8
/EN
Q
8
LEN
Q
0
G
T
Rev.: D
Q
3
Amendment: /0
1
Issue Date: May 2000
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