REGISTERED HEX
PECL-TO-TTL
FEATURES
s
Differential PECL data and clock inputs
s
48mA sink, 15mA source TTL outputs
s
Single +5V power supply
s
Multiple power and ground pins to minimize noise
s
Specified within-device skew
s
V
BB
output for single-ended use
s
Fully compatible with Motorola MC10H/100H607
s
Available in 28-pin PLCC package
SY10H607
SY100H607
DESCRIPTION
The SY10/100H607 are 6-bit, registered, dual supply
PECL-to-TTL translators. The devices feature differential
PECL inputs for both data and clock. The TTL outputs
feature 48mA sink, 15mA source drive capability for
driving high fanout loads. The asynchronous master reset
control is a PECL level input.
With its differential PECL inputs and TTL outputs, the
H607 device is ideally suited for the receive function of a
HPPI bus-type board-to-board interface application. The
on-chip registers simplify the task of synchronizing the
data between the two boards.
The device is available in either ECL standard: the
10H device is compatible with 10K logic levels, while the
100H device is compatible with 100K logic levels.
BLOCK DIAGRAM
PIN CONFIGURATION
V
CCT
Q
4
TGND
Q
5
V
CCT
MR
Q
3
1 OF 6 BITS
D
n
D
n
D
Q
Q
n
Q
2
Q
1
Q
0
25 24 23 22 21 20 19
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
16
D
5
D
5
D
4
D
4
V
CCE
D
3
D
3
CLK
R
TGND
CLK
CLK
V
BB
TOP VIEW
PLCC
15
14
13
12
CLK
D
0
D
0
EGND
D
1
D
1
TTL Outputs
PECL V
CC
(5.0V)
TTL V
CC
(5.0V)
TTL Ground
PECL Ground
V
BB
Reference Output (PECL)
Rev.: F
Amendment: /1
CLK
MR
PIN NAMES
Pin
D
0
鈥?D
5
D
0
鈥?D
5
CLK, CLK
MR
Q
0
鈥?Q
5
V
CCE
V
CCT
TGND
EGND
V
BB
1
Function
True PECL Data Inputs
Inverted PECL Data Inputs
Differential PECL Clock Input
PECL Master Reset Input
V
BB
D
2
D
2
Issue Date: February, 1998
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2
3
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