9-BIT LATCHED
ECL-TO-TTL
SY10H603
SY100H603
FEATURES
s
9-bit ideal for byte-parity applications
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3-state TTL outputs
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Flow-through configuration
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Extra TTL and ECL power/ground pins to minimize
switching noise
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Dual supply
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6.0ns max. delay into 50pF, 12ns into 200pF (all
outputs switching)
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PNP TTL inputs for low loading
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Choice of ECL compatibility: MECL 10KH (10Hxxx)
or 100K (100Hxxx)
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Fully compatible with Motorola MC10H/100H603
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Available in 28-pin PLCC package
DESCRIPTION
The SY10/100H603 are 9-bit, dual supply ECL-to-TTL
translators. Devices in the Micrel-Synergy 9-bit translator
series utilize the 28-lead PLCC for optimal power pinning,
signal flow-through and electrical performance.
The devices feature a 48mA TTL output stage and AC
performance is specified into both a 50pF and 200pF
load capacitance. Latching is controlled by Latch Enable
(LEN) and Master Reset (MR) resets the latches. A HIGH
on OEECL sends the outputs into the high impedance
state. All control inputs are ECL level.
The 10H version is compatible with MECL 10KH ECL
logic levels. The 100H version is compatible with 100K
levels.
PIN CONFIGURATION
GND
V
CCT
GND
Q
7
Q
5
Q
6
BLOCK DIAGRAM
Q
4
26
27
28
1
2
3
4
25 24 23 22 21 20 19
Q
8
OEECL
D
0
D Q
EN
D
1
D Q
EN
D
2
D Q
EN
Q
2
Q
1
Q
0
18
17
16
Q
3
V
CCT
Q
2
GND
Q
1
Q
0
D
8
D
7
V
CCE
D
6
D
5
D
4
D
3
TOP VIEW
PLCC
15
14
13
12
5
6
7
8
9
10 11
D
0
MR
LEN
D
3
D Q
EN
Q
3
ECL
D
4
D Q
EN
Q
4
TTL
PIN NAMES
Q
5
GND
Pin
Function
TTL Ground (0V)
ECL V
CC
(0V)
TTL Supply (+5.0V)
ECL Supply (鈥?.2/鈥?.5V)
Data Inputs (ECL)
Data Outputs (TTL)
3-state Control (ECL)
Latch Enable (ECL)
Master Reset (ECL)
Rev.: D
Amendment: /0
D
5
D Q
EN
D Q
EN
D Q
EN
D Q
EN
D
6
Q
6
V
CCE
V
CCT
D
7
Q
7
V
EE
D
0
鈥揇
8
Q
0
鈥換
8
D
8
LEN
MR
Q
8
OEECL
LEN
MR
1
OEECL
V
EE
D
1
D
2
Issue Date: April, 1998
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