9-BIT LATCHED
TTL-TO-ECL
SY10H602
SY100H602
FEATURES
s
9-bit ideal for byte-parity applications
s
Flow-through configuration
s
Extra TTL and ECL power/ground pins to minimize
switching noise
s
Dual supply
s
3.5ns max. D to Q
s
PNP TTL inputs for low loading
s
Choice of ECL compatibility: MECL 10KH (10Hxxx)
or 100K (100Hxxx)
s
Fully compatible with Motorola MC10H/100H602
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100H602 are 9-bit, dual supply TTL-to-ECL
translators with latches. Devices in the Micrel-Synergy
9-bit translator series utilize the 28-lead PLCC for optimal
power pinning, signal flow-through and electrical
performance.
The H602 features D-type latches. Latching is
controlled by Latch Enable (LEN), while the Master Reset
input resets the latches. A post-latch logic enable is also
provided (ENECL), allowing control of the output state
without destroying latch data. All control inputs are ECL
level.
The 10H version is compatible with MECL 10KH ECL
logic levels. The 100H version is compatible with 100K
levels.
BLOCK DIAGRAM
ENECL
D
0
D Q
EN
D Q
EN
D Q
EN
D Q
EN
D Q
EN
D Q
EN
D Q
EN
D Q
EN
D Q
EN
Q
0
PIN CONFIGURATION
V
CCT
D
3
D
5
D
4
D
2
D
1
D
0
25 24 23 22 21 20 19
D
1
Q
1
D
2
D
6
D
7
D
8
GND
MR
LEN
ENECL
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
16
Q
0
Q
1
V
CCE
V
CCO
Q
2
V
CCO
Q
3
Q
2
TOP VIEW
PLCC
15
14
13
12
D
3
Q
3
Q
8
Q
7
Q
6
V
EE
Q
5
Q
4
ECL
D
5
Q
5
PIN NAMES
Pin
Function
TTL Ground (0V)
ECL V
CC
(0V)
ECL V
CC
(0V) 鈥?Outputs
TTL Supply (+5.0V)
ECL Supply (鈥?.2/鈥?.5V)
Data Inputs (TTL)
Data Outputs (ECL)
Enable Control (ECL)
Latch Enable (ECL)
Master Reset (ECL)
Rev.: D
Amendment: /0
D
6
Q
6
GND
V
CCE
D
7
Q
7
V
CCO
V
CCT
D
8
LEN
MR
Q
8
V
EE
D
0
鈥揇
8
Q
0
鈥換
8
ENECL
LEN
MR
1
V
CCO
Q
4
Issue Date: March, 1998
TTL
D
4
1
2
3
4
