9-BIT ECL-TO-TTL
WITH 3-STATE ENABLE
FEATURES
s
9-bit ideal for byte-parity applications
s
3-state TTL outputs
s
Flow-through configuration
s
Extra TTL and ECL power/ground pins to minimize
switching noise
s
ECL and TTL 3-state control inputs
s
4.8ns max. delay into 50pF, 9.6ns into 200pF (all
outputs switching)
s
PNP TTL inputs for low loading
s
Choice of ECL compatibility: MECL 10KH (10Hxxx)
or 100K (100Hxxx)
s
Fully compatible with Motorola MC10H/100H601
s
Available in 28-pin PLCC package
SY10H601
SY100H601
DESCRIPTION
The SY10/100H601 are 9-bit, dual supply ECL-to-TTL
translators. Devices in the Micrel-Synergy 9-bit translator
series utilize the 28-lead PLCC for optimal power pinning,
signal flow-through and electrical performance.
The devices feature a 48mA TTL output stage and AC
performance is specified into both a 50pF and 200pF
load capacitance. For the 3-state output disable, both
ECL and TTL control inputs are provided, allowing
maximum design flexibility.
The 10H version is compatible with MECL 10KH ECL
logic levels. The 100H version is compatible with 100K
levels.
BLOCK DIAGRAM
OEECL
OETTL
D
0
Q
0
PIN CONFIGURATION
V
CCT
Q
6
GND
Q
5
GND
Q
7
Q
8
25 24 23 22 21 20 19
Q
4
Q
3
V
CCT
Q
2
GND
Q
1
Q
0
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
16
D
8
D
7
V
CCE
D
6
D
5
D
4
D
3
D
1
D
2
Q
1
Q
2
TOP VIEW
PLCC
15
14
13
12
D
3
ECL
D
4
Q
3
Q
4
TTL
OETTL
NC
OEECL
D
0
D
1
D
5
D
6
D
7
Q
5
Q
6
Q
7
PIN NAMES
Pin
GND
V
CCE
Function
TTL Ground (0V)
ECL V
CC
(0V)
TTL Supply (+5.0V)
ECL Supply (鈥?.2/鈥?.5V)
Data Inputs (ECL)
Data Outputs (TTL)
3-State Control (ECL)
3-State Control (TTL)
Rev.: D
Amendment: /0
D
8
Q
8
V
CCT
V
EE
D
0
鈥揇
8
Q
0
鈥換
8
OEECL
OETTL
1
V
EE
D
2
Issue Date: February, 1998
1
2
3
4
