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SY10ELT23 Datasheet

  • SY10ELT23

  • DUAL DIFFERENTIAL PECL-to-TTL TRANSLATOR

  • 4頁

  • MICREL   MICREL

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DUAL DIFFERENTIAL
PECL-to-TTL
TRANSLATOR
FEATURES
s
3.0ns typical propagation delay
s
<500ps typical output-to-output skew
s
Differential PECL inputs
s
24mA TTL outputs
s
Flow-through pinouts
s
Available in 8-pin SOIC package
ClockWorks鈩?/div>
SY10ELT23
SY100ELT23
DESCRIPTION
The SY10/100ELT23 are dual differential PECL-to-TTL
translators. Because PECL (Positive ECL) levels are
used, only +5V and ground are required. The small outline
8-lead SOIC package and the low skew dual gate design
of the ELT23 makes it ideal for applications which require
the translation of a clock and a data signal.
The ELT23 is available in both ECL standards: the
10ELT is compatible with positive ECL 10H logic levels,
while the 100ELT is compatible with positive ECL 100K
logic levels.
PIN CONFIGURATION/BLOCK DIAGRAM
PIN NAMES
Pin
Function
TTL Outputs
Differential PECL Inputs
+5.0V Supply
Ground
D
0
D
0
D
1
D
1
1
2
PECL
3
4
TTL
8
7
6
5
V
CC
Q
0
Q
1
GND
Q
n
D
n
V
CC
GND
SOIC
TOP VIEW
Rev.: G
Amendment: 0
1
Issue Date: December 1999

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