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SY10ELT21ZCTR Datasheet

  • SY10ELT21ZCTR

  • DIFFERENTIAL PECL-to-TTL TRANSLATOR

  • 4頁

  • MICREL   MICREL

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DIFFERENTIAL
PECL-to-TTL
TRANSLATOR
FEATURES
s
2.5ns typical propagation delay
s
Low power
s
Differential PECL inputs
s
24mA TTL outputs
s
Flow-through pinouts
s
Available in 8-pin SOIC package
ClockWorks鈩?/div>
SY10ELT21
SY100ELT21
DESCRIPTION
The SY10/100ELT21 are single differential PECL-to-
TTL translators. Because PECL (Positive ECL) levels are
used, only +5V and ground are required. The small outline
8-lead SOIC package and low skew single gate design
make the ELT21 ideal for applications that require the
translation of a clock or data signal where minimal space,
low power, and low cost are critical.
The V
BB
output allow differential single-ended, or AC-
coupled interface to the device. If used, the V
BB
output
should be bypassed to V
CC
with a 0.01碌F capacitor.
The ELT21 is available in both ECL standards: the
10ELT is compatible with positive ECL 10H logic levels,
while the 100ELT is compatible with positive ECL 100K
logic levels.
PIN CONFIGURATION/BLOCK DIAGRAM
PIN NAMES
Pin
Q
TTL Output
Differential PECL Inputs
+5.0V Supply
Reference Output
Ground
Function
NC 1
D 2
PECL
TTL
8 V
CC
7 Q
6 NC
5 GND
D, /D
V
CC
V
BB
GND
D 3
V
BB
4
SOIC
TOP VIEW
Rev.: B
Amendment: /0
1
Issue Date: April 2000

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