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SY10ELT20V
SY100ELT20V
DESCRIPTION
The SY10/100ELT20V is a single TTL-to-differential
PECL translators. Because PECL (Positive ECL) levels
are used, either +5V or +3.3V and ground are required.
The small outline 8-lead SOIC package and low skew
single gate design make the ELT20V ideal for applications
that require the translation of a clock or data signal where
minimal space, low power, and low cost are critical.
The ELT20V is available in both ECL standards: the
10ELT is compatible with positive ECL 10H logic levels,
while the 100ELT is compatible with positive ECL 100K
logic levels.
PIN CONFIGURATION/BLOCK DIAGRAM
NC 1
Q 2
PECL
TTL
PIN NAMES
Pin
Function
Differential PECL Output
TTL Input
+5V/+3.3V Supply
Ground
8 V
CC
7 D
6 NC
5 GND
Q
D
V
CC
GND
Q 3
NC 4
SOIC
TOP VIEW
Rev.: A
Amendment: /0
1
Issue Date: December 1999