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SY10E457JCTR Datasheet

  • SY10E457JCTR

  • TRIPLE DIFFERENTIAL 2:1 MULTIPLEXER

  • 4頁

  • MICREL   MICREL

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TRIPLE DIFFERENTIAL
2:1 MULTIPLEXER
SY10E457
SY100E457
FEATURES
s
Differential D and Q
s
Extended 100E V
EE
range of 鈥?.2V to 鈥?.5V
s
VBB output for single-ended use
s
700ps max. propagation delay
s
High frequency outputs
s
Separate and common select
s
Internal 75K
鈩?/div>
input pulldown resistors
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E457 are 3-bit differential 2:1
multiplexers. The fully differential data path makes the
devices ideal for multiplexing low skew clock or other
skew sensitive signals. Multiple V
BB
pins are provided to
ease AC coupling input signals.
The higher frequency outputs provide the device with
a >1.0GHz bandwidth to meet the needs of the most
demanding system clock.
Both separate selects and a common select are
provided to make the device well suited for both data
path and random logic applications.
BLOCK DIAGRAM
PIN CONFIGURATION
H
2:1
MUX
SEL
2
D
2a
D
2a
V
BB
Q
0
Q
0
D
0b
D
0b
SEL
0
L
25 24 23 22 21 20 19
SEL
1
D
1a
D
1a
D
2b
COMSEL
D
0a
D
0a
D
2b
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
Q
2
Q
2
V
CC
Q
1
Q
1
Q
0
Q
0
D
1a
D
1a
D
1b
D
1b
SEL
1
H
2:1
MUX
V
EE
Q
1
Q
1
V
BB
D
1b
D
1b
TOP VIEW
PLCC
J28-1
16
15
14
13
12
L
D
0a
D
2a
D
2a
D
2b
D
2b
SEL
2
H
2:1
MUX
Q
2
Q
2
L
PIN NAMES
Pin
D
n
[0:2], D
n
[0:2]
Function
Differential Data Inputs
Individual Select Input
Common Select Input
V
BB
Reference Output
Differential Data Outputs
V
CC
to Output
COMSEL
V
BB
SEL
COMSEL
V
BB
Q[0:2], Q[0:2]
V
CCO
SEL
0
V
CCO
Rev.: C
D
0a
V
BB
D
0b
D
0b
Amendment: /1
1
Issue Date: February, 1998

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