5-BIT DIFFERENTIAL
REGISTER
SY10E452
SY100E452
FEATURES
s
Differential D, CLK and Q
s
Extended 100E V
EE
range of 鈥?.2V to 鈥?.5V
s
VBB output for single-ended use
s
1100MHz min. toggle frequency
s
Asynchronous Master Reset
s
Fully compatible with Motorola MC10E/100E452
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E452 are 5-bit differential registers with
differential data (inputs and outputs) and clock. The
registers are triggered by a positive transition of the
positive clock (CLK) input. A high on the Master Reset
(MR) asynchronously resets all registers so that the Q
outputs go LOW.
The differential input structures are clamped so that
the inputs of unused registers can be left open without
upsetting the bias network of the devices. The clamping
action will assert the /D and the /CLK sides of the inputs.
Because of the edge-triggered flip-flop nature of the
devices, simultaneously opening both the clock and data
inputs will result in an output which reaches an
unidentified but valid state.
The fully differential design of the devices makes them
ideal for very high frequency applications where a
registered data path is necessary.
BLOCK DIAGRAM
D
0
D
0
D
Q
R
D
1
D
1
Q
0
Q
0
PIN CONFIGURATION
V
CCO
Q
4
D
3
D
3
25 24 23 22 21 20 19
D
Q
R
Q
1
Q
1
MR
CLK
CLK
V
EE
V
BB
D
2
D
2
Q
4
D
4
D
4
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
Q
3
Q
3
V
CC
Q
2
Q
2
Q
1
Q
1
TOP VIEW
PLCC
J28-1
16
15
14
13
12
D
2
D
2
D
Q
R
Q
2
Q
2
D
1
D
0
V
CCO
Q
0
D
1
D
0
D
3
D
3
D
Q
R
Q
3
Q
3
PIN NAMES
Pin
D [0:4], /D [0:4]
Function
Differential Data Inputs
Master Reset Input
Differential Clock Input
V
BB
Reference Output
Differential Data Outputs
V
CC
to Output
D
4
D
4
CLK
CLK
MR
V
BB
D
Q
R
Q
4
Q
4
MR
CLK, /CLK
V
BB
Q [0:4], Q [0:4]
V
CCO
Q
0
Rev.: D
Amendment: /0
1
Issue Date: May, 1999
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