700ps max. propagation delay
鈩?/div>
input pull-down resistors
s
Fully compatible with Motorola 10E/100E404
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E404 are 4-bit differential AND/NAND
devices. The differential operation of these devices make
them ideal for pulse shaping applications where duty cycle
skew is critical. Special design techniques were
incorporated to minimize the skew between the upper
and lower level gate inputs.
Because a negative 2-input NAND function is
equivalent to a 2-input OR function, the differential inputs
and outputs of the devices also allow for their use as
fully differential 2-input OR/NOR functions.
The output RISE/FALL times of these devices are
significantly faster than most other standard ECLinPS
devices, resulting in an increased bandwidth.
The differential inputs have clamp structures which
will force the Q output of a gate in an open input condition
to go to a LOW state. Thus, inputs of unused gates can
be left open and will not affect the operation of the rest
of the device.
BLOCK DIAGRAM
D
0a
D
0a
D
0b
D
0b
D
1a
D
1a
D
1b
D
1b
D
2a
D
2a
D
2b
D
2b
D
3a
D
3a
D
3b
D
3b
Q
0
PIN CONFIGURATION
D
3b
V
CCO
Q
3
D
3a
D
3b
D
3a
Q
0
25 24 23 22 21 20 19
Q
1
Q
1
Q
2
Q
2
D
2b
D
2b
D
2a
V
EE
D
2a
D
1b
D
1b
Q
3
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
TOP VIEW
PLCC
J28-1
16
15
14
13
12
Q
2
Q
2
V
CC
Q
1
Q
1
Q
0
Q
0
D
1a
D
1a
D
0a
D
0a
Q
3
Q
3
PIN NAMES
Pin
D[0:4], D[0:4]
Q[0:4], Q[0:4]
V
CCO
Function
Differential Data Inputs
Differential Data Outputs
V
CC
to Output
V
CCO
Rev.: D
D
0b
D
0b
Amendment: /1
1
Issue Date: February, 1998
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