1000ps max. CLK to output
鈩?/div>
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E241
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E241 are 8-bit shiftable registers designed
for use in new, high-performance ECL systems. Unlike the
E141, the E241 features internal data feedback organized
such that the SHIFT control overrides the HOLD, /LOAD
control. Thus, the normal operations of HOLD and LOAD
can be toggled with a single control line without the need for
external gating. This configuration also enables switching
to scan mode with the single SHIFT control line.
The eight inputs D
0
鈥揇
7
accept parallel input data, while
S-IN accepts serial input data when in shift mode. Data is
accepted a set-up time before the rising edge of CLK.
Shifting is also accomplished on the rising clock edge. A
HIGH on the Master Reset pin (MR) asychronously resets
all the registers to zero.
BLOCK DIAGRAM
S-IN
D
D
0
Q
R
Q
0
PIN CONFIGURATION
D
5
V
CCO
SEL
0
NC
D
7
D
6
Q
7
25 24 23 22 21 20 19
SEL
1
CLK
MR
V
EE
S-IN
D
0
D
1
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
Q
6
Q
5
V
CC
NC
V
CCO
Q
4
Q
3
D
D
1
鈥?D
6
Q
R
Q
1
鈥?Q
6
TOP VIEW
PLCC
J28-1
16
15
14
13
12
BITS 1-6
D
2
D
3
D
D
7
SEL
1
(HOLD/LOAD)
SEL
0
(SHIFT)
CLK
MR
Q
R
Q
7
PIN NAMES
Pin
D
0
鈥揇
7
S-IN
SEL
0
SEL
1
CLK
MR
Q
0
鈥換
7
V
CCO
Function
Parallel Data Inputs
Serial Data Input
SHIFT Control
HOLD, /LOAD Control
Clock
Master Reset
Data Outputs
V
CC
to Output
V
CCO
Q
0
Q
1
Q
2
Rev.: C
D
4
Amendment: /1
1
Issue Date: February, 1998
1
2
3
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