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SY10E212JCTR Datasheet

  • SY10E212JCTR

  • 3-BIT SCANNABLE REGISTER

  • 4頁

  • MICREL   MICREL

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3-BIT SCANNABLE
REGISTER
SY10E212
SY100E212
FEATURES
s
Scannable version E112 driver
s
Extended 100E V
EE
range of 鈥?.2V to 鈥?.5V
s
1025ps max. CLK to Output
s
Dual differential outputs
s
Master Reset
s
Internal 75K
鈩?/div>
input pull-down resistors
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Fully compatible with Motorola MC10E/100E212
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E212 are scannable registered ECL
drivers typically used as fan-out memory address drivers
for ECL cache driving. In a VLSI array-based CPU design,
use of the E212 allows the user to conserve array output
cell functionality and also output pins.
The input shift register is designed with control logic
which greatly facilitates its use in boundary scan
applications.
PIN CONFIGURATION
NC
S-OUT
SHIFT
MR
V
CCO
S-OUT
D
Q
D
2
Q
2b
Q
2a
Q
2a
Q
2b
25 24 23 22 21 20 19
LOAD
CLK
D
2
V
EE
D
1
D
0
S-IN
Q
2b
Q
2a
BLOCK DIAGRAM
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
Q
2b
Q
2a
V
CC
Q
1b
Q
1a
Q
1b
Q
1a
TOP VIEW
PLCC
J28-1
16
15
14
13
12
D
Q
D
1
Q
1b
Q
1a
Q
1a
Q
1b
V
CCO
Q
0a
Q
0b
Q
0a
Data Inputs
Scan Input
Scan Control
Clock
Master Reset
Scan Output
True Outputs
D
Q
D
0
S-IN
LOAD
SHIFT
CLK
MR
Q
0b
Q
0a
Q
0a
Q
0b
PIN NAMES
Pin
D
0
鈥?D
2
S-IN
LOAD
SHIFT
CLK
MR
S-OUT
Q[0:2]a, Q[0:2]b
Q[0:2]a, Q[0:2]b
V
CCO
Function
LOAD/HOLD Control
Inverting Outputs
V
CC
to Output
V
CCO
Rev.: C
NC
Q
0b
Amendment: /1
1
Issue Date: February, 1998

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