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SY10E195JCTR Datasheet

  • SY10E195JCTR

  • PROGRAMMABLE DELAY CHIP

  • 78.47KB

  • 8頁

  • MICREL   MICREL

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PROGRAMMABLE
DELAY CHIP
ClockWorks鈩?/div>
SY10E195
SY100E195
FEATURES
s
Up to 2ns delay range
s
Extended 100E V
EE
range of 鈥?.2V to 鈥?.5V
s
鈮?/div>
20ps/digital step resolution
s
>1GHz bandwidth
s
On-chip cascade circuitry
s
75Kk
鈩?/div>
input pulldown resistor
s
Fully compatible with Motorola MC10E/100E195
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E195 are programmable delay chips
(PDCs) designed primarily for clock de-skewing and timing
adjustment. They provide variable delay of a differential
ECL input transition.
The delay section consists of a chain of gates
organized as shown in the logic diagram. The first two
delay elements feature gates that have been modified to
have delays 1.25 and 1.5 times the basic gate delay of
approximately 80ps. These two elements provide the
E195 with a digitally-selectable resolution of
approximately 20ps. The required device delay is selected
by the seven address inputs D[0:6], which are latched
on-chip by a high signal on the latch enable (LEN) control.
If the LEN signal is either LOW or left floating, then the
latch is transparent.
Because the delay programmability of the E195 is
achieved by purely differential ECL gate delays, the
device will operate at frequencies of >1GHz, while
maintaining over 600mV of output swing.
The E195 thus offers very fine resolution, at very high
frequencies, selectable entirely from a digital input,
allowing for very accurate system clock timing.
An eighth latched input, D
7
, is provided for cascading
multiple PDCs for increased programmable range. The
cascade logic allows full control of multiple PDCs, at the
expense of only a single added line to the data bus for
each additional PDC, without the need for any external
gating.
PIN CONFIGURATION
D
7
NC
D
2
D
3
D
4
D
5
D
6
25 24 23 22 21 20 19
D
1
D
0
LEN
V
EE
IN
IN
V
BB
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
TOP VIEW
PLCC
J28-1
16
15
14
13
12
NC
NC
V
CC
V
CCO
Q
Q
V
CCO
EN
SET MIN
SET MAX
CASCADE
NC
NC
CASCADE
PIN NAMES
Pin
IN/IN
EN
D[0:7]
Q/Q
LEN
SET MIN
SET MAX
CASCADE
Function
Signal Input
Input Enable
Mux Select Inputs
Signal Output
Latch Enable
Minimum Delay Set
Maximum Delay Set
Cascade Signal
Rev.: E
Amendment: /0
1
Issue Date: October, 1998

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