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SY10E160JCTR Datasheet

  • SY10E160JCTR

  • 12-BIT PARITY GENERATOR/CHECKER

  • 63.50KB

  • 4頁(yè)

  • MICREL   MICREL

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12-BIT PARITY
GENERATOR/CHECKER
SY10E160
SY100E160
FEATURES
s
Provides odd-HIGH parity of 12 inputs
s
Extended 100E V
EE
range of 鈥?.2V to 鈥?.5V
s
Output register with Shift/Hold capability
s
900ps max. D to Q, /Q output
s
Enable control
s
Asynchronous Register Reset
s
Differential outputs
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal 75K
鈩?/div>
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E160
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E160 are high-speed, 12-bit parity
generator/checkers with differential outputs, for use in
new, high-performance ECL systems. The output Q takes
on a logic HIGH value only when an odd number of inputs
are at a logic HIGH. A logic HIGH on the enable input (EN)
forces the output Q to a logic LOW.
An additional feature of the E160 is the output register.
Two multiplexers and their associated signals control the
register input by providing the option of holding present
data, loading the new parity data or shifting external data
in. To hold the present data, the Hold signal (HOLD) must
be at a logic LOW level. If the HOLD signal is at a logic
HIGH, the data present at the Q output is passed through
the first multiplexer. Taking the Shift signal (SHIFT) to a
logic HIGH will shift the data at the S-IN pin into the output
register. If the SHIFT signal is at a logic LOW, the output
of the first multiplexer is then passed through to the register.
The register itself is clocked on the rising edge of CLK
1
or CLK
2
(or both). The presence of a logic HIGH on the
reset pin (R) forces the register output Y to a logic LOW.
BLOCK DIAGRAM
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
EN
HOLD
S-IN
SHIFT
CLK
1
CLK
2
R
PIN CONFIGURATION
Q
D
4
D
3
D
2
D
1
0
MUX
1
SEL
0
MUX
1
SEL
D
Y
25 24 23 22 21 20 19
Y
R
D
5
D
6
D
7
V
EE
D
8
D
9
D
10
D
1
Q
EN
V
CCO
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
Q
Q
V
CC
Y
Y
V
CCO
NC
PLCC
TOP VIEW
J28-1
16
15
14
13
12
D
11
HOLD
S-IN
SHIFT
CLK
1
CLK
2
R
Rev.: D
Amendment: /0
1
Issue Date: February, 1998

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