550ps max. D to Output
800ps max. SEL to Output
鈩?/div>
input pull-down resistors
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E157 contain four 2:1 multiplexers with
differential outputs. The output data are controlled by the
individual Select (SEL) inputs. The individual select
control makes the devices well suited for random logic
designs.
BLOCK DIAGRAM
PIN CONFIGURATION
V
CCO
SEL
3
NC
D
3a
D
3b
D
0a
1
Q
0
MUX
Q
0
D
2b
D
2a
SEL
2
V
EE
SEL
1
D
1a
D
1b
26
27
28
1
2
3
4
25 24 23 22 21 20 19
18
17
D
0b
SEL
0
D
1a
0
Q
3
Q
3
Q
2
Q
2
V
CC
Q
1
Q
1
Q
0
Q
0
1
Q
1
MUX
Q
1
PLCC
TOP VIEW
J28-1
16
15
14
13
12
D
1b
SEL
1
D
2a
0
5
6
7
8
9
10 11
1
SEL
0
D
0a
D
0b
NC
NC
NC
MUX
D
2b
SEL
2
D
3a
1
0
Q
2
Q
3
MUX
D
3b
SEL
3
Pin
D
0a
鈥?D
3a
D
0b
鈥?D
3b
SEL
0
鈥?SEL
3
Q
0
鈥?Q
3
Q
0
鈥?Q
3
V
CCO
Function
Input Data a
Input Data b
Select Inputs
True Outputs
Inverted Outputs
V
CC
to Output
Q
3
0
PIN NAMES
V
CCO
Rev.: D
Q
2
Amendment: /2
1
Issue Date: May, 1998
1
2
3
4
