900ps max. D to output
800ps max. LEN to output
鈩?/div>
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E156
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E156 offer three 4:1 multiplexers followed
by latches with differential outputs, designed for use in
new, high-performance ECL systems. The two external
latch enable signals (LEN
1
and LEN
2
) are gated through a
logical OR operation before use as control for the three
latches. When both LEN
1
and LEN
2
are at a logic LOW, the
latches are transparent, thus presenting the data from the
multiplexers at the output pins. If either LEN
1
or LEN
2
(or
both) are at a logic HIGH, the outputs are latched.
The multiplexer operation is controlled by the Select
(SEL
0
, SEL
1
) signals which select one of the four bits of
input data at each mux to be passed through.
The MR (Master Reset) signal operates asynchronously
to take all outputs to a logic LOW.
BLOCK DIAGRAM
PIN CONFIGURATION
D
2a
V
CCO
D
1b
D
1a
D
2d
D
2c
D
0a
D
0b
D
0c
D
0d
4:1
MUX
D
E
N R
Q
0
Q
0
SEL
0
SEL
1
MR
26
27
28
1
2
3
4
25 24 23 22 21 20 19
18
17
D
2b
Q
2
Q
2
V
CC
Q
1
Q
1
V
CCO
Q
0
D
1a
D
1b
D
1c
D
1d
D
4:1
MUX
E
N R
Q
1
Q
1
V
EE
LEN
1
LEN
2
D
1c
PLCC
TOP VIEW
J28-1
16
15
14
13
12
5
6
7
8
9
10 11
D
2a
D
2b
D
2c
D
2d
SEL
0
SEL
1
LEN
1
LEN
2
MR
D
4:1
MUX
E
N R
Q
2
Q
2
PIN NAMES
Pin
D
0x
鈥揇
2x
SEL
0
, SEL
1
LEN
1
, LEN
2
MR
Q
0
鈥換
2
Q
0
鈥換
2
V
CCO
Function
Input Data
Select Inputs
Latch Enables
Master Reset
True Outputs
Inverted Outputs
V
CC
to Output
Rev.: C
Amendment: /1
1
V
CCO
Q
0
Issue Date: February, 1998
D
1d
D
0a
D
0b
D
0c
D
0d
1
2
3
4
