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SY10E151JCTR Datasheet

  • SY10E151JCTR

  • 6-BIT D REGISTER

  • 64.78KB

  • 4頁

  • MICREL   MICREL

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6-BIT D
REGISTER
SY10E151
SY100E151
FEATURES
s
1100MHz toggle frequency
s
Extended 100E V
EE
range of 鈥?.2V to 鈥?.46V
s
Differential outputs
s
Asynchronous Master Reset
s
Dual clocks
s
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal 75K
鈩?/div>
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E151
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E151 offer 6 edge-triggered, high-speed,
master-slave D-type flip-flops with differential outputs,
designed for use in new, high-performance ECL systems.
The two external clock signals (CLK
1
, CLK
2
) are gated
through a logical OR operation before use as clocking
control for the flip-flops. Data is clocked into the flip-flops
on the rising edge of either CLK
1
or CLK
2
(or both). When
both CLK
1
and CLK
2
are at a logic LOW, data enters the
master and is transferred to the slave when either CLK
1
or
CLK
2
(or both) go HIGH.
The MR (Master Reset) signal operates asynchronously
to make all Q outputs go to a logic LOW.
BLOCK DIAGRAM
D
0
Q
0
R
D
1
D
R
D
2
D
R
D
3
D
R
D
4
D
R
D
5
D
R
CLK
1
CLK
2
M
R
Q
0
PIN CONFIGURATION
MR
CLK
2
CLK
1
NC
V
CCO
Q
5
Q
5
18
17
D
25 24 23 22 21 20 19
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
D
5
D
4
D
3
V
EE
D
2
D
1
D
0
26
27
28
1
2
3
4
5
6
7
8
9
10 11
Q
4
Q
4
V
CC
Q
3
Q
3
Q
2
Q
2
PLCC
TOP VIEW
J28-1
16
15
14
13
12
V
CCO
Q
0
Q
1
Q
1
Q
4
Q
4
Q
5
Q
5
PIN NAMES
Pin
D
0
鈥揇
5
CLK
1
, CLK
2
MR
Q
0
鈥換
5
Q
0
鈥換
5
V
CCO
Function
Data Inputs
Clock Inputs
Master Reset
True Outputs
Inverting Outputs
V
CC
to Output
V
CCO
Rev.: D
NC
Q
0
Amendment: /0
1
Issue Date: November, 1998

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