700MHz min. operating frequency
鈩?/div>
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E143
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E143 are high-speed 9-bit hold registers
designed for use in new, high-performance ECL systems.
The E143 can hold current data or load new data. The nine
inputs, D
0
-D
8
, accept parallel input data.
The SEL (Select) control pin serves to determine the
mode of operation; either HOLD or LOAD. The input data
has to meet the set-up time before being clocked into the
nine input registers on the rising edge of CLK
1
or CLK
2
.
The MR (Master Reset) control signal asynchronously
resets all nine registers to a logic LOW when a logic HIGH
is applied to MR.
The E143 is designed for applications requiring high-
speed registers, pipeline registers, synchronous operation,
and is also suitable for byte-wide parity.
BLOCK DIAGRAM
MUX
D
R
Q
0
PIN CONFIGURATION
D
0
D
1
MUX
R
25 24 23 22 21 20 19
D
2
MUX
D
R
Q
2
MR
CLK
1
CLK
2
V
EE
NC
D
0
D
1
D
8
D
7
D
6
D
Q
1
D
5
V
CCO
Q
8
SEL
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
Q
7
Q
6
V
CC
Q
5
V
CCO
Q
4
Q
3
D
D
3
MUX
R
Q
3
PLCC
TOP VIEW
J28-1
16
15
14
13
12
D
D
4
MUX
R
Q
4
D
D
5
MUX
R
Q
5
D
D
6
MUX
R
Q
6
PIN NAMES
Pin
Function
Parallel Data Inputs
Mode Select Input
Clock Inputs
Master Reset
Data Outputs
No Connection
V
CC
to Output
D
D
7
MUX
R
Q
7
D
0
-D
8
SEL
D
8
SEL
CLK1
CLK2
MR
MUX
D
R
Q
8
CLK
1
, CLK
2
MR
Q
0
-Q
8
NC
V
CCO
V
CCO
Q
0
Q
1
Q
2
Rev.: D
D
2
D
3
D
4
Amendment: /0
1
Issue Date: August, 1998
1
2
3
4
