700MHz min. shift frequency
鈩?/div>
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E142
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E142 are high-speed 9-bit shift registers
designed for use in new, high-performance ECL systems.
The E142 can accept serial or parallel data to be shifted out
in one direction as both serial and parallel outputs. The
nine inputs, D
0
-D
8
, accept parallel input data, while S-IN
accepts serial input data.
The SEL (Select) control pin serves to determine the
mode of operation, either SHIFT or LOAD. The shift direction
is from bit 0 to bit 8. The input data has to meet the set-up
time before being clocked into the nine input registers on
the rising edge of CLK
1
or CLK
2
. Shifting is also performed
on the rising edge of either CLK
1
or CLK
2
. The MR (Master
Reset) control signal asynchronously resets all nine
registers to a logic LOW when a logic HIGH is applied to
MR.
The E142 is designed for applications such as diagnostic
scan registers, parallel-to-serial conversions and is also
suitable for byte-wide parity.
BLOCK DIAGRAM
S-IN
D
0
1
0
D Q
Q
0
PIN CONFIGURATION
1
D
1
0
D Q
Q
1
1
D
2
0
D Q
Q
2
25 24 23 22 21 20 19
MR
1
D
3
0
D Q
Q
3
D
8
D
7
D
6
D
5
V
CCO
Q
8
SEL
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
Q
7
Q
6
V
CC
Q
5
V
CCO
Q
4
Q
3
1
D
4
0
D Q
Q
4
CLK
1
CLK
2
V
EE
S-IN
D
0
D
1
PLCC
TOP VIEW
J28-1
16
15
14
13
12
1
D
5
0
D Q
Q
5
1
D
6
0
D Q
Q
6
PIN NAMES
D Q
Q
7
1
D
7
0
Pin
D
0
-D
8
V
CCO
1
D
8
SEL
CLK1
CLK2
MR
0
D Q
Q
8
S-IN
SEL
CLK
1
, CLK
2
MR
Q
0
-Q
8
V
CCO
Q
0
Q
1
Q
2
D
2
D
3
D
4
Function
Parallel Data Inputs
Serial Data Input
Mode Select Input
Clock Inputs
Master Reset
Data Outputs
V
CC
to Output
Rev.: C
Amendment: /1
1
Issue Date: February, 1998
1
2
3
4
